SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 128
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Tightly-Coupled Memory Interface
5.5
5.5.1
5.5.2
5-20
TCM interface examples
Zero-wait-state RAM example
Producing byte writable memory using word writable RAM
This section contains the following examples:
•
•
•
Most of the examples in this section are for the DTCM interface. These are also
applicable to the ITCM interface.
The additional logic required for implementing the examples in this section is the
responsibility of the implementer.
Figure 5-12 shows the simplest RAM interface where the RAM block is constructed
from a single word-wide RAM that has byte write control. The TCM interface can
connect directly to the RAM block. This is a zero-wait-state memory so DRWAIT is
tied LOW.
If byte-write RAM is not available, four banks of byte-wide RAM must be used as
shown in Figure 5-13 on page 5-21.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Zero-wait-state RAM example
Producing byte writable memory using word writable RAM
Multiple banks of RAM example on page 5-21.
Note
ARM926EJ-S
Figure 5-12 Zero wait state RAM example
DRADDR[17:0]
DRWD[31:0]
DRSIZE[3:0]
DRWBL[3:0]
DRRD[31:0]
DRWAIT
DRnRW
DRIDLE
DRSEQ
DRCS
[14:0]
b0110
CLK
CLK
A[14:0]
DIN[31:0]
nRW
BW[3:0]
CS
DOUT[31:0]
ARM DDI0198D
RAM 32KB
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