SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 217
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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ARM DDI0198D
31
SBZ
2.
3.
4.
To write an entry into the lockdown TLB, the full sequence is therefore:
To read an entry from the lockdown TLB, the entry must first be written using the above
instructions. The entry can then be read using the following instructions:
29
Bit
[31:29]
[28:26]
[25:0]
28
Indexed
Copyright © 2001-2003 ARM Limited. All rights reserved.
entry
Table B-8 describes the entry-select bit fields in the Rd register.
Use the following MMU Test Register instructions to access the MVA tag:
See Figure B-3 on page B-7 for read or write data in the Rd register.
Use the following MMU Test Register instructions to read or write the PA and
access permission data:
See Figure B-4 on page B-8 for the read or write data in the Rd register.
Use the following instruction to complete a write to an entry:
26
25
-
Indexed entry
-
Name
Table B-8 Encoding of the lockdown TLB entry-select bit fields
Figure B-6 Rd format for selecting lockdown TLB entry
Definition
Should Be Zero
Indexed entry in lockdown TLB
Should Be Zero
SBZ
CP15 Test and Debug Registers
B-11
0
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