SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 95
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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3.7
ARM DDI0198D
TLB structure
The MMU contains a single unified TLB used for both data accesses and instruction
fetches. The TLB is divided into two parts:
•
•
Whether an entry is placed in the set-associative, or lockdown part of the TLB is
dependent on the state of the TLB lockdown register, when the entry is written into the
TLB (see TLB Lockdown Register c10 on page 2-32).
When an entry has been written into the lockdown part of the TLB, it can only be
removed by being overwritten explicitly, or by an MVA-based TLB invalidate
operation, where the MVA matches the locked down entry.
The structure of the set-associative part of the TLB does not form part of the
programmer's model for the ARM926EJ-S processor. No assumptions must be made
about the structure, replacement algorithm, or persistence of entries in the
set-associative part. Specifically:
•
•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
an eight-entry fully-associative part used exclusively for holding locked down
TLB entries
a set-associative part for all other entries, 2 way x 32 entry.
Any entry written into the set-associative part of the TLB can be removed at any
time. The set-associative part of the TLB must be considered as a temporary cache
of translation/page table information. No reliance must be placed on an entry
either residing or not residing in the set-associative TLB, unless that entry already
exists in the lockdown TLB. The set-associative part of the TLB can contain
entries that are defined in the page tables but do not correspond to address values
that have been accessed since the TLB was invalidated.
The set-associative part of the TLB must be considered as a cache of the
underlying page table, where memory coherency must be maintained at all times.
If a level one descriptor is modified in main memory, then to guarantee coherency
either an invalidate TLB or invalidate TLB by entry operation must be used to
remove any cached copies of the level one descriptor. This is required regardless
of the type of level one descriptor (section, level two page table reference, or
fault).
If any of the subpage permissions for a given page are different, then each of the
subpages are treated separately. To invalidate all the entries associated with a page
with subpage permissions then four MVA-based invalidate operations are
required, one for each subpage.
Memory Management Unit
3-31
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