SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 220
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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CP15 Test and Debug Registers
B-14
31
Bit
[31:8]
[7]
[6]
[5]
[4]
You can access the MMU Debug Control Register using the following instructions:
The MMU Debug Control Register format is shown in Figure B-8.
The MMU Debug Control Register bit assignments are given in Table B-10. The reset
value of the MMU Debug Control Register is
Copyright © 2001-2003 ARM Limited. All rights reserved.
Name
-
DMTMI
DMTMD
DMTLI
DMTLD
Function
Reserved
Disable main TLB matching for
instruction fetches
Disable main TLB matching for data
accesses
Disable main TLB load because of
instruction fetch miss
Disable main TLB load because of
data access miss
SBZ
Table B-10 MMU Debug Control Register bit assignments
Figure B-8 MMU Debug Control Register format
.
DMTMD
DDUTM
DMTLD
DDUTL
DMTMI
DIUTM
DMTLI
DIUTL
Description
Read = Unpredictable
Write = Should Be Zero
0 = Enable matching
1 = Disable matching
0 = Enable matching
1 = Disable matching
0 = Enable TLB load
1 = Disable TLB load
0 = Enable TLB load
1 = Disable TLB load
8
7
6
5
4
ARM DDI0198D
3 2
1
0
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