SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 164
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Coprocessor Interface
8.4
8-8
CDP
nCPMREQ is driven LOW to signal when an instruction is entering the Decode and
then the Execute stage of the pipeline. If the instruction is to be executed then the
CPPASS signal is driven HIGH during Execute. If the coprocessor can execute the
instruction immediately it drives CHSDE[1:0] with LAST. If the instruction requires a
busy-wait cycle, then the coprocessor drives CHSDE[1:0] with WAIT and then
CHSEX[1:0] with LAST. Figure 8-6 shows a CDP that is canceled due to the previous
instruction causing a Data Abort.
The CDP instruction enters the Execute stage of the pipeline and is signaled to execute
by CPPASS. In the following phase CPLATECANCEL is asserted. This causes the
coprocessor to terminate execution of the CDP instruction and for it to cause no state
changes to the coprocessor.
CPLATECANCEL can be asserted during the Memory cycle or during the Execute
cycle. The coprocessor must be able to handle instruction aborts during these two
stages.
instructions usually execute in a single cycle. Like all the previous cycles,
Copyright © 2001-2003 ARM Limited. All rights reserved.
Note
Coprocessor pipeline
CPLATECANCEL
CPINSTR[31:0]
CHSDE[1:0]
CHSEX[1:0]
nCPMREQ
CPPASS
CLK
CPRT
Fetch
Decode
LAST
Execute
Ignored
Figure 8-6 Latecanceled CDP
Memory
ARM DDI0198D
Instruction
aborted
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