SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 166
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SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Coprocessor Interface
8.6
8-10
Busy-waiting and interrupts
Coprocessor pipeline
CPLATECANCEL
CPINSTR[31:0]
The coprocessor is permitted to stall (busy-wait) the processor during the execution of
a coprocessor instruction if, for example, it is still busy with an earlier coprocessor
instruction. To do so, the coprocessor associated with the Decode stage instruction
drives WAIT on CHSDE[1:0]. When the instruction concerned enters the Execute stage
of the pipeline, the coprocessor can drive WAIT onto CHSEX[1:0] for as many cycles
as required to keep the instruction in the busy-wait loop.
For interrupt latency reasons the coprocessor might be interrupted while busy-waiting,
causing the instruction to be abandoned using CPPASS. The coprocessor must monitor
the state of CPPASS during every busy-wait cycle. If it is HIGH the instruction must be
executed. If it is LOW the instruction must be abandoned.
Figure 8-8 shows a busy-waited coprocessor instruction being abandoned due to an
interrupt.
In Figure 8-8, CPLATECANCEL is also asserted as a result of the Execute
interruption.
CHSDE[1:0]
CHSEX[1:0]
nCPMREQ
CPPASS
CLK
Copyright © 2001-2003 ARM Limited. All rights reserved.
CPInstr
Fetch
Decode
WAIT
Execute
(WAIT)
WAIT
Figure 8-8 Busy waiting and interrupts
Execute
(WAIT)
WAIT
Execute
(WAIT)
WAIT
interrupted
ARM DDI0198D
Execute
Ignored
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