AD5737 Analog Devices, AD5737 Datasheet
AD5737
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AD5737 Summary of contents
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... DAC with Dynamic Power Control and HART Connectivity 7 29.5 V using a dc-to-dc boost converter optimized for minimum on-chip power dissipation. Each channel has a corresponding CHART pin so that HART signals can be coupled onto the current output of the AD5737. The AD5737 at clock rates MHz and is compatible with standard SPI, QSPI™ ...
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... Reprogramming the Output Range ......................................... 24 Data Registers ............................................................................. 25 REVISION HISTORY 11/11—Rev Rev. A Change to Accuracy, External R Parameter in Table 1 ............ 4 SET Changes to Power-On State of the AD5737 Section .................. 21 Changes to Readback Operation Section and Readback Example Section.............................................................................. 30 7/11—Revision 0: Initial Version Control Registers ........................................................................ 27 Readback Operation .................................................................. 30 ...
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... AD1 DAC CHANNEL C AD5737 DAC CHANNEL D AD0 SW DYNAMIC 7.4V TO 29.5V V POWER CONTROL DAC INPUT DAC A REG Figure 2. Rev Page AD5737 V A BOOST_A DC-TO-DC CONVERTER V SEN1 SEN2 R3 I OUT_A R SET_A CHARTA OUT_B OUT_C OUT_D SET_B SET_C ...
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... AD5737 SPECIFICATIONS 2 5 BOOST_x DD REFIN = 300 Ω; all specifications T L Table 1. 1 Parameter Min CURRENT OUTPUT Output Current Ranges Resolution 12 ACCURACY, EXTERNAL R SET Total Unadjusted Error (TUE) −0.1 TUE Long-Term Stability Relative Accuracy (INL) −0.032 Differential Nonlinearity (DNL) − ...
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... BOOST Rev Page AD5737 Test Conditions/Comments At 10 kHz Drift after 1000 hours 150°C J See Figure 41 See Figure 42 See Figure 41 First temperature cycle Second temperature cycle This oscillator is divided down to provide the ...
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... AD5737 AC PERFORMANCE CHARACTERISTICS 2 5 BOOST_x DD REFIN = 300 Ω; all specifications T L Table 2. 1 Parameter DYNAMIC PERFORMANCE, CURRENT OUTPUT Output Current Settling Time Output Noise (0 Bandwidth) Output Noise Spectral Density 1 Guaranteed by design and characterization; not production tested. ...
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... LSB Figure 3. Serial Interface Timing Diagram LSB MSB MSB Figure 4. Readback Timing Diagram Rev Page LSB NOP CONDITION LSB SELECTED REGISTER DATA t CLOCKED OUT 15 AD5737 ...
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... AD5737 LSB 1 2 SCLK SYNC DUT_ DUT_ X R/W SDIN AD1 AD0 SDO SDO DISABLED X X D15 D14 SDO_ STATUS STATUS ENAB Figure 5. Status Readback During Write, Timing Diagram 200µ (MIN OUTPUT OH PIN V (MAX 50pF 200µ Figure 6. Load Circuit for SDO Timing Diagrams Rev ...
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... THERMAL RESISTANCE Junction-to-air thermal resistance (θ 4-layer test board Table 5. Thermal Resistance Package Type BOOST_x 64-Lead LFCSP (CP-64-3) ESD CAUTION )/θ Rev Page AD5737 ) is specified for a JEDEC JA θ Unit JA 20 °C/W ...
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... SYNC. If LDAC is held high during the write cycle, the DAC input register is updated, but the DAC output is updated only on the falling edge of LDAC (see updated simultaneously. The PIN 1 1 SET_B 2 SET_A 3 4 AD0 5 AD1 6 AD5737 SYNC 7 SCLK 8 TOP VIEW SDIN 9 (Not to Scale) SDO ...
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... Channel C dc-to-dc converter. Alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin. For more information, see the DC-to-DC Converter Compensation Capacitors section and the AI Supply Requirements—Slewing section. CC Supply Requirements—Slewing section. CC Supply Requirements—Slewing section. CC Rev Page AD5737 ...
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... AD5737 Pin No. Mnemonic Description 49 IGATEC Optional Connection for External Pass Transistor. Leave this pin unconnected when using the dc-to-dc converter. For more information, see the External PMOS Mode section Connect. Do not connect to this pin. 51 CHARTC HART Input Connection for DAC Channel C. For more information, see the HART Connectivity section. ...
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... TO 24mA RANGE MIN INL 0mA TO 20mA RANGE MIN INL –40 – TEMPERATURE (°C) MAX DNL 0 MIN DNL AV = 15V DD ALL RANGES INTERNAL AND EXTERNAL R SET –40 – TEMPERATURE (°C) Figure 13. Differential Nonlinearity Error vs. Temperature AD5737 80 100 SET = 15V 80 100 SET 80 100 ...
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... AD5737 0.025 0.020 0.015 0.010 0.005 0 –0.005 AV = 15V –0.010 DD –0.015 4mA TO 20mA RANGE, INTERNAL R –0.020 4mA TO 20mA RANGE, EXTERNAL R –0.025 –40 – TEMPERATURE (°C) Figure 14. Total Unadjusted Error vs. Temperature 0.020 0.015 0.010 0.005 0 –0.005 ...
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... OUT_x V BOOST_x 0mA TO 24mA RANGE 1kΩ LOAD f = 410kHz SW INDUCTOR = 10µH (XAL4040-103 25° –0.50 –0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 TIME (ms) Figure 25. Output Current and V Settling Time BOOST_x with DC-to-DC Converter (See Figure 55) AD5737 = 15V DD = 25°C = 300Ω LOAD 15V = 300Ω ...
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... AD5737 –40° +25° +105° 0mA TO 24mA RANGE 1kΩ LOAD 410kHz SW INDUCTOR = 10µH (XAL4040-103 –0.25 0 0.25 0.50 0.75 1.00 TIME (ms) Figure 26. Output Current Settling Time with DC-to-DC Converter over Temperature (See Figure 55 4. ...
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... TO 24mA RANGE 1kΩ LOAD EXTERNAL R SET 410kHz SW INDUCTOR = 10µH (XAL4040-103) 20 –40 – TEMPERATURE (°C) Figure 35. Output Efficiency vs. Temperature (See Figure 55) 0.6 0.5 0.4 0.3 0.2 0.1 0 –40 – TEMPERATURE (°C) Figure 36. Switch Resistance vs. Temperature AD5737 80 100 80 100 ...
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... Figure 40. REFOUT Voltage vs. Temperature (When the AD5737 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. ...
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... Supply Voltage ( 25° 14.4 14.2 14.0 13.8 13.6 13 25°C 13 0mA OUT 13 Figure 46. Internal Oscillator Frequency vs Rev Page 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12 5.5V DD 12.6 –40 – TEMPERATURE (°C) Figure 45. Internal Oscillator Frequency vs. Temperature T = 25°C A 2.5 3.0 3.5 4.0 4.5 VOLTAGE (V) DD AD5737 80 100 5.0 5.5 Supply Voltage ...
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... The V considered part of the dc-to-dc converter’s losses. × I OUT AV CC Rev Page Data Sheet pin for which the output current is equal to the AD5737 is powered on specified as the quiescent current is considered BOOST_x R LOAD × BOOST_x is defined as the ratio of the power ...
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... MSB first as a 24-bit word under the control of the serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. If packet error checking (PEC) is enabled, an additional eight bits must be written to the AD5737, creating a 32-bit serial interface (see the Packet Error Checking section). V ...
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... AD5737 TRANSFER FUNCTION For the mA mA, and current output ranges, the output current is expressed by the following equations: For the range ⎛ ⎞ ⎜ ⎜ ⎟ ⎟ × OUT N ⎝ ⎠ 2 For the range ⎛ ...
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... Data Sheet REGISTERS Table 7, Table 8, and Table 9 provide an overview of the registers for the AD5737. Table 7. Data Registers for the AD5737 Register Description DAC Data Registers The four DAC data registers (one register per DAC channel) are used to write a DAC code to each DAC channel ...
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... AD5737 ENABLING THE OUTPUT To correctly write to and set up the part from a power-on condition, use the following sequence: 1. Perform a hardware or software reset after initial power-on. 2. Configure the dc-to-dc converter supply block. Set the dc-to-dc switching frequency, the maximum output voltage allowed, and the dc-to-dc converter phase between channels. ...
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... Write to a control register DAC_AD0 DAC Channel 0 DAC A 1 DAC B 0 DAC C 1 DAC D D20 D19 D18 Rev Page D17 D16 DAC_AD1 DAC_AD0 AD5737 device is being D17 D16 D15 to D4 DAC_AD1 DAC_AD0 DAC data AD5737 LSB D15 to D0 Data ...
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... AD5737 Gain Register The 12-bit gain register allows the user to adjust the gain of each channel in steps of 1 LSB. To write to the gain register of one DAC channel, set the DREG[2:0] bits to 010 (see Table 13). To write the same gain code to all four DAC channels at the same time, set the DREG[2:0] bits to 011 ...
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... DAC control register (one per channel) 1 DC-to-DC control register 0 Software register D10 EWD WD1 WD0 X X Timeout Period (ms 100 200 Rev Page AD5737 D15 D14 D13 CREG2 CREG1 CREG0 OUTEN_ALL DCDC_ALL LSB D12 to D0 Data ...
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... AD5737 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 22 and Table 23. Table 22. Programming the DAC Control Register D15 D14 D13 D12 D11 D10 don’t care. ...
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... Table 26 and Table 27. D13 D12 0 User program Description Writing 0x555 to Bits[D11:D0] performs a software reset of the AD5737. If the watchdog timer feature is enabled, 0x195 must be written to the software register (Bits[D11:D0]) within the programmed timeout period (see Table 21). D12 ...
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... Read DAC C slew rate control register 1 1 Read DAC D slew rate control register 0 0 Read status register 0 1 Read main control register 1 0 Read dc-to-dc control register Rev Page Data Sheet AD5737 Device 1, Channel SR_CLOCK SR_STEP LSB D17 D16 D15 RD1 RD0 X ...
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... OUT_B pin. OUT_A Rev Page OUT_D OUT_C fault fault Functionality section for MAX Functionality section for MAX Functionality section for MAX Functionality section for MAX AD5737 LSB OUT_B OUT_A fault fault ...
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... C is the code in the offset register (default code = 2 STATUS READBACK DURING A WRITE The AD5737 the status register during every write sequence. This feature is enabled using the STATREAD bit in the main control register. When this feature is enabled, the user can continuously monitor the status register and act quickly in the case of a fault ...
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... V voltage reference with value. To improve the stability of the output current SET resistor, R1, can be bypassed SET pin of the AD5737. The external resistor is selected SET_x resistor and an external, 15 kΩ R SET resistor allows for improved SET resistor option. The external ...
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... Table 1, Figure 45, and Figure 46). Table 35. Slew Rate Step Size Options SR_STEP 000 001 010 011 100 AD5737 allows the 101 110 111 The following equation describes the slew rate as a function of the step size, the update clock frequency, and the LSB size. Slew ...
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... TO 24mA RANGE, 24mA OUTPUT MAX DC-DCx BIT OUTPUT UNLOADED DC-DC MaxV BITS = 29.5V DC-DCx BIT = 410kHz 25°C A DC-DCx BIT = 0 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (ms) Figure 56. Operation on Reaching V MAX AD5737 ramps up to the V − ~0.4 V. MAX AD5737 input of 4 Headroom), × LOAD pin OUT_x , if still 3.5 4.0 value but MAX ...
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... The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5737, a low ESR tantalum or ceramic supply of 4 capacitor of 10 μF is recommended for typical applications. CC Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature ...
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... External 51 kΩ Compensation Resistor AI CC 0mA TO 24mA RANGE I OUT V BOOST f SW INDUCTOR = 10µH (XAL4040-103 0.5 1.0 1.5 2.0 TIME (ms) Current vs. Time for 24 mA Step Through 500 Ω Load CC with External 51 kΩ Compensation Resistor AD5737 pin DCDC_x 2 500Ω LOAD = 410kHz 25° ...
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... SW DAC A EXTERNAL PMOS MODE The per channel, as shown in Figure 61. This mode can be used to limit the on-chip power dissipation of the AD5737, although this 32 mode does not reduce the power dissipation of the total system. 28 The IGATEx functionality is not typically required when using the dynamic power control feature; therefore, Figure 61 shows ...
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... A 0.01 μF capacitor between I ensures stability of a load of 50 mH. The capacitive component of the load may cause slower settling, although this may be masked by the settling time of the AD5737. There is no maxi- mum capacitance limit for the current output of the AD5737. Long-Term Drift ...
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... SPORT interface AD5737 SPORT_TFS SYNC SPORT_TSCLK SCLK SPORT_DT0 SDIN ADSP-BF527 GPIO0 LDAC Figure 63. AD5737-to-ADSP-BF527 SPORT Interface AD5737 is mounted should be designed so that the AD5737 system where pin and the ground connection for the AV x should have ample supply bypassing of 10 μF CC ...
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... ADuM1411. For ADuM1411 V SERIAL CLOCK IA ENCODE DECODE OUT V SERIAL DATA IB ENCODE DECODE OUT V IC SYNC OUT ENCODE DECODE V ID CONTROL OUT ENCODE DECODE Figure 64. 4-Channel Isolated Interface to the AD5737 AD5737 ) to SW DCDC x AD5737 SCLK SDIN SYNC LDAC ...
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... AD5737 OUTLINE DIMENSIONS PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Resolution (Bits) AD5737ACPZ 12 AD5737ACPZ-RL7 RoHS Compliant Part. 9.00 BSC SQ 0.60 MAX 49 48 0.50 8.75 BSC BSC SQ 0.50 0. 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.20 REF 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 Figure 65. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ × ...
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... Data Sheet NOTES Rev Page AD5737 ...
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... AD5737 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10067-0-11/11(A) Rev Page Data Sheet ...