AD5737 Analog Devices, AD5737 Datasheet - Page 35

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

Data Sheet
When the slew rate control feature is enabled, all output changes
occur at the programmed slew rate (see the DC-to-DC Converter
Settling Time section for more information). For example, if the
CLEAR pin is asserted, the output slews to the clear value at the
programmed slew rate (assuming that the channel is enabled to
be cleared).
If more than one channel is enabled for digital slew rate control,
care must be taken when asserting the CLEAR pin. If a channel
under slew rate control is slewing when the CLEAR pin is asserted,
other channels under slew rate control may change directly to
their clear code not under slew rate control.
DYNAMIC POWER CONTROL
The
a dc-to-dc boost converter circuit. This circuit reduces power
consumption compared with standard designs.
In standard current input module designs, the load resistor
values can range from typically 50 Ω to 750 Ω. Output module
systems must source enough voltage to meet the compliance
voltage requirement across the full range of load resistor values.
For example, in a 4 mA to 20 mA loop when driving 20 mA, a
compliance voltage of >15 V is required. When driving 20 mA
into a 50 Ω load, a compliance voltage of only 1 V is required.
The
this voltage to meet the compliance requirements plus a small
headroom voltage. The
24 mA through a 1 kΩ load.
DC-TO-DC CONVERTERS
The
These are used to provide dynamic control of the V
voltage for each channel (see Figure 48). Figure 55 shows the
discrete components needed for the dc-to-dc circuitry, and the
following sections describe component selection and operation
of this circuitry.
Table 36. Recommended Components for a DC-to-DC Converter
Symbol
L
C
D
It is recommended that a 10 Ω, 100 nF low-pass RC filter be
placed after C
but reduces the amount of ripple on the V
DCDC
DCDC
DCDC
AD5737
AD5737
AD5737
AV
CC
≥10µF
C
Component
XAL4040-103
GRM32ER71H475KA88L
PMEG3010BEA
IN
provides integrated dynamic power control using
circuitry senses the output voltage and regulates
contains four independent dc-to-dc converters.
DCDC
. This filter consumes a small amount of power
L
10µH
DCDC
Figure 55. DC-to-DC Circuit
SW
AD5737
x
D
C
4.7µF
DCDC
DCDC
is capable of driving up to
R
FILTER
10Ω
Value
10 μH
4.7 μF
0.285 V
BOOST_x
F
C
0.1µF
FILTER
V
supply.
BOOST_x
Manufacturer
Coilcraft®
Murata
NXP
BOOST_x
supply
Rev. A | Page 35 of 44
DC-to-DC Converter Operation
The on-board dc-to-dc converters use a constant frequency, peak
current mode control scheme to step up an AV
to 5.5 V to drive the
are designed to operate in discontinuous conduction mode with
a duty cycle of <90% typical. Discontinuous conduction mode
refers to a mode of operation where the inductor current goes
to zero for an appreciable percentage of the switching cycle. The
dc-to-dc converters are nonsynchronous; that is, they require an
external Schottky diode.
DC-to-DC Converter Output Voltage
When a channel current output is enabled, the converter regulates
the V
whichever is greater (see Figure 30 for a plot of headroom supplied
vs. output current). When the output is disabled, the converter
regulates the V
DC-to-DC Converter Settling Time
The settling time for a step greater than ~1 V (I
dominated by the settling time of the dc-to-dc converter. The
exception to this is when the required voltage at the I
plus the compliance voltage is below 7.4 V (±5%). Figure 25
shows a typical plot of the output settling time. This plot is for
a 1 kΩ load. The settling time for smaller loads is faster. The
settling time for current steps less than 24 mA is also faster.
DC-to-DC Converter V
The maximum V
register (23 V, 24.5 V, 27 V, or 29.5 V; see Table 27). When the
maximum voltage is reached, the dc-to-dc converter is disabled,
and the V
V
reenabled, and the voltage ramps up again to V
required. This operation is shown in Figure 56.
As shown in Figure 56, the DC-DCx bit in the status register
is asserted when the
is deasserted when the voltage decays to V
BOOST_x
BOOST_x
29.6
29.5
29.4
29.3
29.2
29.1
29.0
28.9
28.8
28.7
28.6
voltage decays by ~0.4 V, the dc-to-dc converter is
0
BOOST_x
DC-DCx BIT = 1
DC-DCx BIT = 0
supply to 7.4 V (±5%) or (I
V
DC-DCx BIT
MAX
BOOST_x
0.5
Figure 56. Operation on Reaching V
voltage is allowed to decay by ~0.4 V. After the
BOOST_x
AD5737
AD5737
1.0
supply to 7.4 V (±5%).
voltage is set in the dc-to-dc control
MAX
1.5
Functionality
output channel. These converters
ramps up to the V
TIME (ms)
DC-DC MaxV BITS = 29.5V
0mA TO 24mA RANGE, 24mA OUTPUT
OUTPUT UNLOADED
f
T
2.0
SW
A
= 25°C
= 410kHz
OUT
2.5
× R
MAX
3.0
LOAD
MAX
− ~0.4 V.
CC
MAX
OUT
MAX
input of 4.5 V
+ Headroom),
, if still
3.5
× R
value but
AD5737
OUT_x
LOAD
4.0
pin
) is