AD5737 Analog Devices, AD5737 Datasheet - Page 27

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

Data Sheet
CONTROL REGISTERS
When writing to a control register, the format shown in Table 18
must be used. See Table 11 for information about the configura-
tion of Bit D23 to Bit D16. The control registers are addressed
by setting the DREG[2:0] bits (Bits[D20:D18] in the input shift
register) to 111 and then setting the CREG[2:0] bits to select the
specific control register (see Table 19).
Table 18. Input Shift Register for a Write Operation to a Control Register
MSB
D23
R/W
Table 19. Control Register Addresses (CREG[2:0] Bits)
CREG2 (D15)
0
0
0
0
1
Table 20. Programming the Main Control Register
D15
0
1
Table 21. Main Control Register Bit Descriptions
Bit Name
STATREAD
EWD
WD1, WD0
OUTEN_ALL
DCDC_ALL
X = don’t care.
D14
0
D22
DUT_AD1
D13
1
Description
Enable status readback during a write. See the Status Readback During a Write section.
0 = disable status readback (default).
1 = enable status readback.
Enable the watchdog timer. See the Watchdog Timer section.
0 = disable the watchdog timer (default).
1 = enable the watchdog timer.
Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1
0
0
1
1
Setting this bit to 1 enables the output on all four DACs simultaneously. Do not use the OUTEN_ALL bit when using the
OUTEN bit in the DAC control register.
Setting this bit to 1 powers up the dc-to-dc converter on all four channels simultaneously. To power down the dc-to-dc
converters, all channel outputs must first be disabled. Do not use the DCDC_ALL bit when using the DC_DC bit in the
DAC control register.
D21
DUT_AD0
CREG1 (D14)
0
0
1
1
0
D12
0
WD0
0
1
0
1
D20
1
D11
STATREAD
D19
1
CREG0 (D13)
0
1
0
1
0
Timeout Period (ms)
5
10
100
200
D10
EWD
D18
1
D9
WD1
Rev. A | Page 27 of 44
D8
WD0
D17
DAC_AD1
Control Register
Slew rate control register (one per channel)
Main control register
DAC control register (one per channel)
DC-to-DC control register
Software register
Main Control Register
The main control register options are shown in Table 20 and
Table 21. See the Device Features section for more information
about the features controlled by the main control register.
D7
X
1
D16
DAC_AD0
D6
X
1
D15
CREG2
D5
OUTEN_ALL DCDC_ALL
D14
CREG1
D4
D13
CREG0
AD5737
D12 to D0
Data
D3 to D0
X
1
LSB