AD5737 Analog Devices, AD5737 Datasheet - Page 26

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

AD5737
Gain Register
The 12-bit gain register allows the user to adjust the gain of
each channel in steps of 1 LSB. To write to the gain register of
one DAC channel, set the DREG[2:0] bits to 010 (see Table 13).
To write the same gain code to all four DAC channels at the
same time, set the DREG[2:0] bits to 011. The gain register
coding is straight binary, as shown in Table 14. The default code
in the gain register is 0xFFFF. The maximum recommended
gain trim is approximately 50% of the programmed range to
maintain accuracy (for more information, see the Digital Offset
and Gain Control section).
Offset Register
The 12-bit offset register allows the user to adjust the offset
of each channel by −2048 LSB to +2047 LSB in steps of 1 LSB.
To write to the offset register of one DAC channel, set the
Table 13. Programming the Gain Register
R/W
0
Table 14. Gain Register Bit Descriptions
Gain Adjustment
+4096 LSB
+4095 LSB
…
1 LSB
0 LSB
Table 15. Programming the Offset Register
R/W
0
Table 16. Offset Register Bit Descriptions
Offset Adjustment
+2047 LSB
+2046 LSB
…
No Adjustment (Default)
…
−2047 LSB
−2048 LSB
Table 17. Programming the Clear Code Register
R/W
0
DUT_AD1
DUT_AD1
DUT_AD1
Device address
Device address
Device address
DUT_AD0
DUT_AD0
DUT_AD0
G15
1
1
…
0
0
OF15
1
1
…
1
…
0
0
DREG2
0
DREG2
1
DREG2
1
G14
1
1
…
0
0
OF14
1
1
…
0
…
0
0
DREG1
1
DREG1
0
DREG1
1
Rev. A | Page 26 of 44
DREG0
0
DREG0
0
DREG0
0
G13 to G5
111111111
111111111
…
000000000
000000000
OF13
1
1
…
0
…
0
0
DREG[2:0] bits to 100 (see Table 15). To write the same offset
code to all four DAC channels at the same time, set the DREG[2:0]
bits to 101. The offset register coding is straight binary, as shown in
Table 16. The default code in the offset register is 0x8000, which
results in zero offset programmed to the output (for more infor-
mation, see the Digital Offset and Gain Control section).
Clear Code Register
The 12-bit clear code register allows the user to set the clear
value of each channel. To configure a channel to be cleared
when the CLEAR pin is activated, set the CLR_EN bit in the
DAC control register for that channel (see Table 23). To write
to the clear code register, set the DREG[2:0] bits to 110 (see
Table 17). The default clear code is 0x0000 (for more informa-
tion, see the Asynchronous Clear section).
DAC_AD1
DAC_AD1
DAC_AD1
DAC channel address
DAC channel address
DAC channel address
OF12 to OF5
11111111
11111111
…
00000000
…
00000000
00000000
DAC_AD0
DAC_AD0
DAC_AD0
OF4
1
0
…
…
1
0
G4
1
0
…
1
0
0
D15 to D4
D15 to D4
D15 to D4
Gain adjustment
Offset adjustment
Clear code
Data Sheet
G3 to G0
1111
1111
1111
1111
1111
OF3 to OF0
0000
0000
0000
0000
0000
0000
0000
D3 to D0
1111
D3 to D0
D3 to D0
0000
0000