AD5737 Analog Devices, AD5737 Datasheet - Page 21

• Manufacturer Part Number: AD5737
• Description: Quad Channel, 12-Bit, Serial Input, 4-20mA Output DAC with Dynamic Power Control and HART Connectivity
• Manufacturer: Analog Devices

Specifications of AD5737

• Resolution (bits): 12bit
• Dac Settling Time: 15µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

Data Sheet
THEORY OF OPERATION
The
designed to meet the requirements of industrial process control
applications. It provides a high precision, fully integrated, low cost,
single-chip solution for generating current loop outputs. The
current ranges available are 0 mA to 20 mA, 4 mA to 20 mA,
and 0 mA to 24 mA. The output configuration is user-selectable
via the DAC control register.
On-chip dynamic power control minimizes package power
dissipation (see the Dynamic Power Control section).
DAC ARCHITECTURE
The DAC core architecture of the
matched DAC sections. A simplified circuit diagram is shown
in Figure 47. The four MSBs of the 12-bit data-word are decoded
to drive 15 switches, E1 to E15. Each switch connects one of
15 matched resistors either to ground or to the reference buffer
output. The remaining eight bits of the data-word drive Switch S0
to Switch S7 of an 8-bit voltage mode R-2R ladder network.
The voltage output from the DAC core is converted to a current,
which is then mirrored to the supply rail so that the application
sees only a current source output (see Figure 48). The current
outputs are supplied by V
Reference Buffers
The
reference. The reference input requires a 5 V reference for
specified performance. This input voltage is then buffered
before it is applied to the DAC.
AD5737
AD5737
2R
8-BIT R-2R LADDER
12-BIT
Figure 48. Voltage-to-Current Conversion Circuitry
DAC
2R
S0
is a quad, precision digital-to-current loop converter
can operate with either an external or internal
S1
2R
Figure 47. DAC Ladder Structure
A1
BOOST_x
S7
2R
T1
FOUR MSBs DECODED INTO
.
15 EQUAL SEGMENTS
R2
R
SET
AD5737
2R
E1
A2
T2
V
E2
BOOST_x
2R
consists of two
R3
I
OUT_x
2R
E15
V
OUT
Rev. A | Page 21 of 44
POWER-ON STATE OF THE AD5737
When the
tristate mode. After a device power-on or a device reset, it is
recommended that the user wait at least 100 μs before writing to
the device to allow time for internal calibrations to take place.
SERIAL INTERFACE
The
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of the serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking (PEC) is enabled, an additional eight
bits must be written to the AD5737, creating a 32-bit serial
interface (see the Packet Error Checking section).
The DAC outputs can be updated in one of two ways: individual
DAC updating or simultaneous updating of all DACs.
Individual DAC Updating
To update an individual DAC, LDAC is held low while data is
clocked into the DAC data register. The addressed DAC output
is updated on the rising edge of SYNC . See Table 3 and Figure 3
for timing information.
Simultaneous Updating of All DACs
To update all DACs simultaneously, LDAC is held high while
data is clocked into the DAC data register. After LDAC is taken
high, only the first write to the DAC data register of each channel
is valid; subsequent writes to the DAC data register are ignored,
although these subsequent writes are returned if a readback is
initiated. All DAC outputs are updated by taking LDAC low
after SYNC is taken high.
AD5737
Figure 49. Simplified Serial Interface of the Input Loading Circuitry
V
REFIN
LDAC
SYNC
SCLK
SDIN
AD5737
is controlled by a versatile 3-wire serial interface
is first powered on, the I
DAC INPUT
INTERFACE
REGISTER
DAC DATA
REGISTER
REGISTER
for One DAC Channel
12-BIT
DAC
LOGIC
DAC
AMPLIFIERS
CALIBRATION
OUTPUT
AND GAIN
OFFSET
SDO
OUT_x
I
pins are in
OUT_x
AD5737