ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 156

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

Serial peripheral interface (SPI)
Note:
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SPIE = 1 in the SPICR register. It is cleared by a software sequence (an access to the
SPICSR register followed by a write or a read to the SPIDR register).
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Bit 6 = WCOL Write Collision status (Read only)
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see
Bit 5 = OVR SPI Overrun error (Read only)
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (see
(OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared
by software reading the SPICSR register.
Bit 4 = MODF Mode Fault flag (Read only)
This bit is set by hardware when the SS pin is pulled low in master mode (see
fault
is cleared by a software sequence (An access to the SPICSR register while MODF = 1
followed by a write to the SPICR register).
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output Disable
This bit is set and cleared by software. When set, it disables the alternate function of the SPI
output (MOSI in master mode / MISO in slave mode)
Bit 1 = SSM SS Management
This bit is set and cleared by software. When set, it disables the alternate function of the SPI
SS pin and uses the SSI bit value instead. See
Bit 0 = SSI SS Internal Mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the
SS slave select signal when the SSM bit is set.
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the device and an external device has been completed.
0: No write collision occurred
1: A write collision has been detected
0: No overrun error
1: Overrun error detected
(MODF)). An SPI interrupt can be generated if SPIE = 1 in the SPICR register. This bit
0: No master mode fault detected
1: A fault in master mode has been detected
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
0: Slave selected
1: Slave deselected
Doc ID 12370 Rev 8
Slave select
Figure
75).
management.
Overrun condition
ST72561-Auto
Master mode