ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 169

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
15.8
15.8.1
Note:
Note:
The SCI interrupt events are connected to the same interrupt vector (see Interrupts
chapter).
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
SCI mode register description
Status register (SCISR)
Read only
Reset value: 1100 0000 (C0h)
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the TDR register has been transferred into
the shift register. An interrupt is generated if the TIE = 1 in the SCICR2 register. It is cleared
by a software sequence (an access to the SCISR register followed by a write to the SCIDR
register).
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a character containing Data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the SCIDR register).
TC is not set after the transmission of a Preamble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the RDR register has been transferred to the
SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a read to the SCIDR
register).
Bit 4 = IDLE Idle line detected.
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if the
ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to the
SCISR register followed by a read to the SCIDR register).
The IDLE bit will not be set again until the RDRF bit has been set itself (that is, a new idle
line occurs).
Bit 3 = OR Overrun error
TDRE
0: data is not transferred to the shift register
1: data is transferred to the shift register
0: transmission is not complete
1: transmission is complete
0: data is not received
1: received data is ready to be read
0: no Idle Line is detected
1: idle Line is detected
7
TC
RDRF
LINSCI serial communication interface (LIN master/slave)
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