ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 236

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

beCAN controller (beCAN)
236/324
Therefore if: t
the application will never wait in the workaround
t
the CAN interrupt level
t
t
actual location of the workaround
t
Figure 111. Critical window timing diagram
Figure 112. Reception of a sequence of frames
Side-effect of workaround 1
Because the while loop lasts 10 CPU cycles, at high baud rate, it is possible to miss a
dominant state on the bus if it lasts just one CAN bit time and the bus speed is high enough
(see
Table 84.
If this happens, we will continue waiting in the while loop instead of releasing the FIFO
immediately. The workaround is still valid because we will not release the FIFO during the
IT higher level
IT disable
IT CAN
CAN frame
Table
8 MHz
4 MHz
f
f
: This is the maximum duration between the beginning of the CAN interrupt and the
CPU
CPU
FMP
BUS
CPU
: This is the longest time the application disables the CAN interrupt (or all interrupts)
: This is minimum CAN frame duration
84).
: This the sum of the duration of all the interrupts with a level strictly higher than
While loop timing
IT higher level
t
CAN frame
Acknowledge: last
dominant bit in the frame
Software timing: while loop
0
+ t
Time to test RX pin and to
release the FIFO 4.5µs@4 MHz Time between the end of the
1
IT disable
Doc ID 12370 Rev 8
1.25 µs
10/f
2.5 µs
CPU
+ t
CAN Frame
IT CAN
t
IT disable
t
CAN frame
1
< 2 x t
acknowledge and the critical windows
- 6 full CAN bit times + time to the sample point
approx. 13µs @ 500 Kbaud
2
Critical window: the received
message is placed in the FIFO
CAN frame
t
IT higher level
Minimum baud rate for possible
missed dominant bit
t
CAN frame
2
800 Kbaud
400 Kbaud
f
A release is not
allowed at this time
CPU
t
IT CAN
3
/10
ST72561-Auto
2