ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 226

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

beCAN controller (beCAN)
Note:
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Mask/Identifier registers is configured by means of the FMCLx and FMCHx bits in the CFMR
register. The FMCLx bit defines the mode for the two least significant bytes, and the FMCHx
bit the mode for the two most significant bytes of filter bank x.
Example 1:
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In 32-bit configuration, the FMCLx and FMCHx bits must have the same value to ensure that
the four Mask/Identifier registers are in the same mode.
To filter a group of identifiers, configure the mask/identifier registers in mask mode.
To select single identifiers, configure the mask/identifier registers in identifier list mode.
Filters not used by the application should be left deactivated.
Filter match index
Once a message has been received in the FIFO it is available to the application. Typically
application data are copied into RAM locations. To copy the data to the right location the
application has to identify the data by means of the identifier. To avoid this and to ease the
access to the RAM locations, the CAN controller provides a filter match index.
This index is stored in the mailbox together with the message according to the filter priority
rules. Thus each received message has its associated Filter Match Index.
The Filter Match Index can be used in two ways:
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For non-masked filters, the software no longer has to compare the identifier.
If the filter is masked the software reduces the comparison to the masked bits only.
Filter priority rules
Depending on the filter combination it may occur that an identifier passes successfully
through several filters. In this case the filter match value stored in the receive mailbox is
chosen according to the following rules:
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Figure
If filter bank 1 is configured as two 16-bit filters, then the FMCL1 bit defines the mode of
the CF1R2 and CF1R3 registers and the FMCH1 bit defines the mode of the CF1R6
and CF1R7 registers.
If filter bank 2 is configured as four 8-bit filters, then the FMCL2 bit defines the mode of
the CF2R1 and CF2R3 registers and the FMCH2 bit defines the mode of the CF2R5
and CF2R7 registers.
Compare the filter match Index with a list of expected values.
Use the filter match index as an index on an array to access the data destination
location.
A filter in identifier list mode prevails on an filter in mask mode.
A filter with full identifier coverage prevails over filters covering part of the identifier, e.g.
16-bit filters prevail over 8-bit filters.
Filters configured in the same mode and with identical coverage are prioritized by filter
number and register number. The lower the number the higher the priority.
102. The identifier list or identifier mask mode for the corresponding
Doc ID 12370 Rev 8
ST72561-Auto