71M6543G Maxim, 71M6543G Datasheet - Page 106

• Manufacturer Part Number: 71M6543G
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6543F/H and 71M6543G/GH Data Sheet
106
Name
DIO_EEX[1:0]
DIO_PV
DIO_PW
DIO_PX
DIO_PY
EEDATA[7:0]
EECTRL[7:0]
EQU[2:0]
Location Rst Wk Dir
2456[7:6]
2106[7:5]
SFR 9E
SFR 9F
2457[6]
2457[7]
2458[7]
2458[6]
0
0
0
0
0
0
0
0
–
–
–
–
–
0
0
0
© 2008–2011 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
When set, converts SEGDIO3 and SEGDIO2 to interface with external EEPROM.
SEGDIO2 becomes SDCK and SEGDIO3 becomes bi-directional SDATA, but only if
LCD_MAP[2] and LCD_MAP[3] are cleared.
Causes VPULSE to be output on SEGDIO1, if LCD_MAP[1]=0.
Causes WPULSE to be output on SEGDIO0, if LCD_MAP[0]=0.
Causes XPULSE to be output on SEGDIO6 , if LCD_MAP[6]=0.
Causes YPULSE to be output on SEGDIO7 , if LCD_MAP[7]=0.
Serial EEPROM interface data.
Serial EEPROM interface control.
Specifies the power equation.
DIO_EEX[1:0]
EQU[2:0]
Note:
*The available CE codes implements only equation 5. Contact your local Teridian representative to obtain
CE code for equation 3 and 4.
Status
Bit
5*
7
6
5
3
4
00
01
10
11
ERROR
BUSY
RX_ACK
Name
2 element, 4W,
2 element, 4W,
3 element, 4W,
Description
3φ Del a
Function
Disable EEPROM interface
2-Wire EEPROM interface
3-Wire EEPROM interface
3-Wire EEPROM interface with separate DO (SEGDIO3) and DI
(SEGDIO8) pins.
3φ Wye
3φ ye
Read/
Write
R
R
R
Reset
State
0
0
1
VA(IA-IB)/2
Element
VA(I -IB)/
VA IA
0
Polarity Description
Positive 1 when an illegal command is received.
Positive 1 when serial data bus is busy.
Positive
VB(IC-IB)/2
Element
1 indicates that the EEPROM sent an
ACK bit.
VB IB
1
0
Element
VC C
VC IC
2
0
Recommended
MUX Sequence
IA VA IB B
IA A IB VB IC V
IA VA IB V
I VC
C VC
v1.2