71M6543G Maxim, 71M6543G Datasheet - Page 29

• Manufacturer Part Number: 71M6543G
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
Figure 11
and 0x2108[7:0]), consisting of 1819 samples of 457.8 µs each, followed by the XFER_BUSY interrupt.
The sampling in this example is applied to a 50 Hz signal. There is no correlation between the line signal
frequency and the choice of SUM_SAMPS[12:0]. Furthermore, sampling does not have to start when the
line voltage crosses the zero line, and the length of the accumulation interval need not be an integer
multiple of the signal cycles.
v1.2
(32768 Hz)
STATE
CK32
MUX
S
shows the accumulation interval resulting from SUM_SAMPS[12:0] = 1819 (I/O RAM 0x2107[4:0]
61.04 µs
20ms
IA
0
Figure 10: Samples from Multiplexer Cycle (Frame)
61.04 µs
© 2008–2011 Teridian Semiconductor Corporation
VA
1
Figure 11: Accumulation Interval
IB
2
833ms
Multiplexer Frame (15 x 30.518 µs = 457.8 µs)
MUX_DIV
= 7 Conversions
VB
3
71M6543F/H and 71M6543G/GH Data Sheet
IC
4
61.04 µs
VC
5
Interrupt to MPU
XFER_BUSY
61.04 µs
ID
6
30.5 µs
Settle
S
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