71M6543G Maxim, 71M6543G Datasheet - Page 84

• Manufacturer Part Number: 71M6543G
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

MPU is in reset due to the internal WAKE signal being low. When the Wake Timer times out, WAKE rises
and within three CK32 cycles, the MPU begins to execute. The MPU can determine that the timer woke it
by checking the WF_TMR (I/O RAM 0x28B1[2]) wake flag.
The Wake Timer begins timing when the part enters LCD or SLP mode. Its duration is controlled by the
WAKE_TMR[7:0] register (I/O RAM 0x2880). The timer duration is WAKE_TMR[7:0] +1 seconds.
71M6543F/H and 71M6543G/GH Data Sheet
Note:
“WAKE falls” implies that the internal WAKE signal has been reset, which happens automatically upon
entry into LCD mode or SLEEP mode (i.e., when the MPU sets the LCD_ONLY bit (I/O RAM 0x28B2[6]) or
the SLEEP (I/O RAM 0x28B2[7]) bit). When the internal WAKE signal resets, all wake flags are reset. Since
the various wake flags are automatically reset when WAKE falls, it is not necessary for the MPU to reset
these flags before entering LCD mode or SLEEP mode. Also, other wake events can cause the wake flag
to reset, as indicated above (e.g., the WF_RST flag can also be reset by any of the following flags setting:
WF_CSTART, WS_RSTBIT, WF_OVF, WF_BADVDD)
3.4.2 Wake on Timer
If the part is in SLP or LCD mode, it can be awakened by the Wake Timer. Until this timer times out, the
The Wake Timer is armed by setting WAKE_ARM = 1 (I/O RAM 0x28B2[5]). It must be armed at least
three RTC cycles before either SLP or LCD modes are initiated. Setting WAKE_ARM presets the timer
with the value in WAKE_TMR and readies the timer to start when the MPU writes to the SLEEP (I/O RAM
0x28B2[7]) or LCD_ONLY (I/O RAM 0x28B2[6]) bits. The timer is neither reset nor disarmed when the
MPU wakes-up. Thus, once armed and set, the MPU continues to be awakened WAKE_TMR[7:0]
seconds after it requests SLP mode or LCD mode (i.e., once written, the WAKE_TMR[7:0] register holds
its value and does not have to be re-written each time the MPU enters SLP or LCD mode. Also, since
WAKE_TMR[7:0] is non-volatile, it also holds its value through resets and power failures).
3.5
The data flow between the Compute Engine (CE) and the MPU is shown in
the 32-bit CE sequentially processes the samples from the ADC inputs, performing calculations to measure
84
WF_CSTART
WF_RSTBIT
WF_DIO52
WF_DIO55
WF_DIO4
WF_ERST
WF_TMR
WF_OVF
WF_RST
WF_PB
WF_RX
Flag
Data Flow and MPU/CE Communication
RESET pin driven high
RESET bit is set (I/O RAM 0x2200[3])
Watchdog (WD) reset
Timer expiration
PB pin high level
Either edge RX pin
SEGDIO4 rising edge
SEGDIO52 high level
If OPT_RXDIS = 1 (I/O RAM 0x2457[2]),
wake on SEGDIO55 high
If OPT_RXDIS = 0
wake on either edge of OPT_RX
E_RST pin driven high and the ICE
interface must be enabled by driving the
ICE_E pin high.
Cold-start (i.e., after the application of
first power)
© 2008–2011 Teridian Semiconductor Corporation
Table 66: Clear Events for WAKE flags
Wake on:
Clear Events
WAKE falls
WAKE falls
WAKE falls
WAKE falls
WAKE falls
WAKE falls
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_OVF, WF_BADVDD
WAKE falls, WF_CSTART, WF_OVF,
WF_BADVDD, WF_RST
WAKE falls, WF_CSTART, WF_RST,
WF_OVF, WF_RSTBIT
WAKE falls, WF_CSTART, WF_RSTBIT,
WF_BADVDD, WF_RST
WAKE falls, WF_RSTBIT, WF_OVF,
WF_BADVDD, WF_RST
Figure
26. In a typical application,
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