71M6543G Maxim, 71M6543G Datasheet - Page 68

• Manufacturer Part Number: 71M6543G
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6543F/H and 71M6543G/GH Data Sheet
2.5.12 SPI Slave Port
The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM
and Configuration RAM (I/O RAM) locations. It is also able to send commands to the MPU. The interface
to the slave port consists of the SPI_CSZ, SPI_CKI, SPI_DI and SPI_DO pins. These pins are multiplexed
with the combined DIO/LCD segment driver pins SEGDIO36 to SEGDIO39 (pins 3, 2, 1 and 100).
Additionally, the SPI interface allows flash memory to be read and to be programmed. To facilitate flash
programming, cycling power or asserting RESET causes the SPI port pins to default to SPI mode. The
SPI port is disabled by clearing the SPI_E bit (I/O RAM 0x270C[4]).
Possible applications for the SPI interface are:
68
SDATA output Z
SDATA (output)
EECTRL Byte Written
SCLK (output)
Write -- With HiZ and WFR
Write -- No HiZ
BUSY (bit)
SDATA output Z
SDATA output Z
SDATA (input)
EECTRL Byte Written
SCLK (output)
SDATA output Z
SDATA (output)
SDATA (out/in)
EECTRL Byte Written
SCLK (output)
EECTRL Byte Written
SCLK (output)
Write -- With HiZ
BUSY (bit)
BUSY (bit)
BUSY (bit)
READ
Figure 22: 3-wire Interface. Write Command when HiZ=1 and WFR=1.
Figure 21: 3-Wire Interface. Write Command when CNT=0
D7
INT5 not issued
Figure 19: 3-wire Interface. Write Command, HiZ=1
© 2008–2011 Teridian Semiconductor Corporation
Figure 20: 3-wire Interface. Read Command.
(LoZ)
D7
D7
CNT Cycles (0 shown)
D7
D6
D6
D6
CNT Cycles (8 shown)
(From 6520)
CNT Cycles (6 shown)
CNT Cycles (6 shown)
(HiZ)
(LoZ)
(LoZ)
D5
D5
D5
SDATA output Z
SDATA (output)
EECTRL Byte Written
SCLK (output)
D4
BUSY (bit)
Write -- HiZ
D4
D4
D3
D3
D3
D2
D2
INT5 not issued
D2
INT5
(From EEPROM)
(HiZ)
(HiZ)
(HiZ)
BUSY
D1
CNT Cycles (0 shown)
D0
INT5
READY
INT5
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