71M6543G Maxim, 71M6543G Datasheet - Page 71

• Manufacturer Part Number: 71M6543G
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

elements such as XRAM and IO RAM are not accessible in this mode. In order to protect the flash
contents, several operations are required before the SFM mode is successfully invoked.
In SFM mode, the 71M6543 supports n byte reads and dual-byte writes to flash memory. See the
Transaction
operation is always based on a two-byte word, the initial address must always be even. Data is written to
the 16-bit flash memory bus after the odd word is written.
When the 71M6543G/GH is operating SFM, SPI single-byte transactions are used to write to
FL_BANK[1:0] (SFR 0xB6[1:0]). During an SPI single-byte transaction, SPI_CMD[1:0] will over-write the
contents of FL_BANK[1:0] (SFR 0xB6[1:0]). This will allow for access of the entire 128 KB flash memory
while operating in SFM.
In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI
Transaction section above is not available in SFM mode. The 71M6543 must be reset by the WD timer or
by the RESET pin in order to exit SFM mode.
Invoking SFM
The following conditions must be met prior to invoking SFM:
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The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only
the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for
SPI Flash Mode (SFM)
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6543 supports a special flash mode (SFM) which facilitates initial programming of the flash memory.
When the 71M6543 is in this mode, the SPI can erase, read, and write the flash memory. Other memory
v1.2
Name
SPI_STAT
ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent
Flash corruption.
The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC).
PREBOOT = 0 (SFR 0xB2[7]). This validates the state of the SECURE bit (SFR 0xB2[6]).
SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
FLSH_UNLOCK[3:0] = 0010 (I/O RAM 0x2702[7:4]).
description on Page
Location
2708[7:0]
© 2008–2011 Teridian Semiconductor Corporation
Rst
0
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Wk
0
for the format of read and write commands. Since the flash write
Dir
R
Description
SPI_STAT contains the status results from the previous
SPI transaction
Bit 7 - 71M6543 ready error: the 71M6543 was not
ready to read or write as directed by the previous
command.
Bit 6 - Read data parity: This bit is the parity of all bytes
read from the 71M6543 in the previous command. Does
not include the SPI_STAT byte.
Bit 5 - Write data parity: This bit is the overall parity of
the bytes written to the 71M6543 in the previous
command. It includes CMD and ADDR bytes.
Bit 4:2 - Bottom 3 bits of the byte count. Does not
include ADDR and CMD bytes. One, two, and three
byte instructions return 111.
Bit 1 - SPI FLASH mode: This bit is zero when the
TEST pin is zero.
Bit 0 - SPI FLASH mode ready: Used in SPI FLASH
mode. Indicates that the flash is ready to receive
another write instruction.
71M6543F/H and 71M6543G/GH Data Sheet
SPI
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