71M6543G Maxim, 71M6543G Datasheet - Page 40

• Manufacturer Part Number: 71M6543G
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

71M6543F/H and 71M6543G/GH Data Sheet
2.4.8 WD Timer (Software Watchdog Timer)
There is no internal software watchdog timer. Use the standard hardware watchdog timer instead (see
2.5.13 Hardware Watchdog
2.4.9 Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own interrupt request
flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the
corresponding flag can be individually enabled or disabled by the enable bits in IEN0 (SFR 0xA8), IEN1
(SFR 0xB8), and IEN2 (SFR 0x9A).
Referring to
Internal Sources) or can originate from other parts of the 71M6543 SoC (referred to as External Sources).
There are seven external interrupt sources, as seen in the leftmost part of
Table 27
Interrupt Overview
When an interrupt occurs, the MPU vectors to the predetermined address as shown in
the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service
is terminated by a return from instruction, RETI. When an RETI is performed, the processor returns to the
instruction that would have been next when the interrupt occurred.
When the interrupt condition occurs, the processor also indicates this by setting a flag bit. This bit is set
regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per
machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt when
the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt is
acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following conditions
are met:
•
•
•
Special Function Registers for Interrupts
The following SFR registers control the interrupt functions:
•
40
TCON[7]
TCON[6]
TCON[5]
TCON[4]
TCON[3]
TCON[2]
TCON[1]
TCON[0]
No interrupt of equal or higher priority is already in progress.
An instruction is currently being executed and is not completed.
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.
The interrupt enable registers: IEN0, IEN1 and IEN2 (see
Bit
(i.e., EX0-EX6).
Figure 12,
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Symbol
Table 25: The TCON Register Bit Functions (SFR 0x88)
interrupt sources can originate from within the 80515 MPU core (referred to as
© 2008–2011 Teridian Semiconductor Corporation
Timer).
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when an
interrupt is processed.
Timer 1 run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt
is processed.
Timer 0 Run control bit. If cleared, Timer 0 stops.
Interrupt 1 edge flag is set by hardware when the falling edge on external
pin int1 is observed. Cleared when an interrupt is processed.
Interrupt 1 type control bit. Selects either the falling edge or low level on
input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external
pin int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. Selects either the falling edge or low level on
input pin to cause interrupt.
Figure 12
shows the device interrupt structure.
Table
Function
26,
Table 27
Figure
and
12, and in
Table
Table
28).
Table 26
38. Once
and
v1.2