TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 228

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

3.11.2
(1) Memory access control
Bank Activate
Precharge All
Read
Read with Auto Precharge
Write
Write with Auto Precharge
Mode Register Set
Burst Stop
Auto Refresh
Self Refresh Entry
Self Refresh Exit
address area, the SDRAMC outputs SDRAM control signals.
SDRAM access cycles is controlled by the SDRAMC and does not depend on the number of
waits controlled by the memory controller.
(a)
Note 1: H = High level, L = Low level, RA = Row address, CA = Column address, M = Mode data, X = Don’t care
Note 2: CKE n = CKE level in the command input cycle
The SDRAMC is enabled by setting SDACR<SMAC> to “1”.
When one of the bus masters (CPU, LCDC, DMAC) generates a cycle to access the SDRAM
Figure 3.11.2 to Figure3.11.5 shows the timing for accessing the SDRAM. The number of
Command
issues commands automatically for each SDRAM access cycle generated by each bus
master.
Operation Description
The SDRAMC issues commands as specified by the SDCMM register. The SDRAMC also
Table 3.11.1 shows the commands that are issued by the SDRAMC.
Command issue function
CKE n-1 = CKE level in a cycle immediately before the command input cycle
Table 3.11.1 Commands Issued by the SDRAMC
CKEn-1
H
H
H
H
H
H
H
H
H
H
L
CKEn
H
H
H
H
H
H
H
H
H
H
L
92CF29A-226
SDxxDQM
H
H
H
H
H
H
H
L
L
L
L
A10
RA
H
H
H
L
L
L
X
X
X
X
A15-11
A9-0
RA
CA
CA
CA
CA
M
X
X
X
X
X
SDCS
H
L
L
L
L
L
L
L
L
L
L
SDRAS SDCAS SDWE
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
TMP92CF29A
2009-06-11
H
H
H
H
H
H
L
L
L
L
L