TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 4

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

(11) I
(12) LCD controller
(13) SDRAM controller:1 channel
(14) Timer for real-time clock (RTC)
(15) Key-on wakeup (Interrupt key input)
(16) 10-bit A/D converter (Built in Sample Hold circuit): 6 channels
(17) Touch screen interface
(18) Watchdog timer
(19) Melody/alarm generator
(20) MMU
(21) Interrupts: 57 interrupts
(22) DMAC function: 6 channels
(23) Input/Output ports: 98 pins (Except Data bus (16bit), Address bus (24bit) and
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2
S (Inter-IC Sound) interface: 1 channel
9 CPU interrupts: Software interrupt instruction and illegal instruction
39 internal interrupts: Seven selectable priority levels
9 external interrupts: Seven selectable priority levels (include key interrupt)
I
Data Format is supported Left/Right Justify
128-byte FIFO buffer (64 bytes × 2)
Supports monochrome, 4, 16 and 64 gray levels and 256/4096/65536 colors for STN
Supports monochrome, 4096/65536 colors for TFT
Supports PIP (Picture In Picture Display)
Supports H/W Rotation function for support to various LCDM
Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate)
Possible to execute instruction on SDRAM
Based on TC8521A
Built-in Switch of Low-resistor, and available to reduce external components for shift
Melody: Output of a clock 4 to 5461-Hz clock
Alarm: Output of 8 kinds of alarm pattern
5 kinds of interval interrupt
Expandable up to 2.1 Gbytes (3 local area/8 bank method)
Independent bank for each program, read data, write data, source and destination of
High-speed data transfer enable by controlling which convert micro DMA function and
SDRAM
change row/column
DMAC (Odd channel/Even channel) and LCD display data
this function
2
S bus mode selectable (Master, transmission only)
(8-edge selectable)
92CF29A-2
TMP92CF29A
RD
2009-06-11
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