adc1010s125hn/c1 NXP Semiconductors, adc1010s125hn/c1 Datasheet
adc1010s125hn/c1
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adc1010s125hn/c1 Summary of contents
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ADC1010S series Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 01 — 9 April 2010 1. General description The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number f (Msps) Package s ADC1010S125HN/C1 125 ADC1010S105HN/C1 105 ADC1010S080HN/C1 80 ADC1010S065HN/ Block diagram INP INM Fig 1. Block diagram ADC1010S_SER_1 Preliminary data sheet ADC1010S series; CMOS or LVDS DDR digital outputs Name Description HVQFN40 plastic thermal enhanced very thin quad flat package; ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning terminal 1 index area REFB 1 REFT 2 3 AGND 4 VCM VDDA 5 ADC1010S HVQFN40 AGND 6 INM 7 8 INP 9 AGND VDDA 10 Transparent top view Fig 2. Pin configuration with CMOS digital outputs selected 6.2 Pin description Table 2. Symbol REFB REFT AGND VCM ...
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... NXP Semiconductors Table 2. Symbol n.c. n.c. n.c. n.c. DAV n.c. VDDO OGND OTR SCLK/DFS SDIO/ODS CS SENSE VREF [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. Table 3. Symbol D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P n.c. n.c. n.c. ADC1010S_SER_1 Preliminary data sheet ADC1010S series; CMOS or LVDS DDR digital outputs ...
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... NXP Semiconductors Table 3. Symbol n.c. DAVM DAVP [1] Pins and pins are the same for both CMOS and LVDS DDR outputs (see [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7. Limiting values Table 4. In accordance with the Absolute Maximum Rating System (IEC 60134). ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics Symbol Parameter Supplies V analog supply voltage DDA V output supply voltage DDO I analog supply current DDA I output supply current DDO P power dissipation Clock inputs: pins CLKP and CLKM LVPECL V differential clock input voltage i(clk)dif LVDS ...
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... NXP Semiconductors Table 6. Static characteristics Symbol Parameter Digital outputs, CMOS mode: pins D9 to D0, OTR, DAV Output levels DDO V LOW-level output voltage OL V HIGH-level output voltage OH I LOW-level output current OL I HIGH-level output current OH C output capacitance O Output levels 1.8 V DDO ...
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Dynamic characteristics 10.1 Dynamic characteristics [1] Table 7. Dynamic characteristics Symbol Parameter Conditions Analog signal processing α second MHz - 2H i harmonic MHz - i level MHz - i ...
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Table 7. Dynamic characteristics …continued Symbol Parameter Conditions IMD Intermodulati MHz - i on distortion MHz - MHz - 170 MHz - i [1] Typical values ...
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Clock and digital output timing Table 8. Clock and digital output timing characteristics Symbol Parameter Conditions Min Clock timing input: pins CLKP and CLKM f clock frequency 20 clk t data latency clock cycles - lat(data) time δ clock ...
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... NXP Semiconductors Fig Fig 5. ADC1010S_SER_1 Preliminary data sheet ADC1010S series; CMOS or LVDS DDR digital outputs d(s) t clk CLKP CLKM − 14) DATA DAV t CMOS mode timing d(s) t clk CLKP CLKM − 14 ...
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... NXP Semiconductors 10.3 SPI timings Table 9. Symbol t w(SCLK) t w(SCLKH) t w(SCLKL clk(max) [1] Typical values measured at V values are across the full temperature range T Fig 6. 11. Application information 11.1 Device control The ADC1010S can be controlled via SPI or directly via the I/O pins (PIN control mode). ...
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... NXP Semiconductors Fig 7. Control mode selection When the device enters SPI control mode, the output data standard and data format are determined by the level on pin SDIO at the instant a transition is triggered by a falling edge on CS. 11.1.2 Operating mode selection The active ADC1010S operating mode (Power-up, Power-down or Sleep) can be selected ...
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... NXP Semiconductors Fig 8. The sample phase occurs when the internal clock (derived from the clock signal on pin CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the clock signal goes LOW, the stage enters the hold phase and the voltage information is transmitted to the ADC core ...
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... NXP Semiconductors Table 11. Input frequency 3 MHz 70 MHz 170 MHz 11.2.3 Transformer The configuration of the transformer circuit is determined by the input frequency. The configuration shown in Fig 10. Single transformer configuration suitable for baseband applications The configuration shown in both cases, the choice of transformer will be a compromise between cost and performance ...
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... NXP Semiconductors 11.3 System reference and power management 11.3.1 Internal/external references The ADC1010S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale. This reference voltage can be set internally via SPI or with pins VREF and SENSE (programmable steps between 0 dB and −6 dB via control bits INTREF[2:0] when bit INTREF_EN = 1 ...
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... NXP Semiconductors Figure 13 required reference voltage source. VREF 330 pF REFERENCE EQUIVALENT SCHEMATIC SENSE Fig 13. Internal reference (p-p) full-scale VREF 0.1 μF V REFERENCE EQUIVALENT SCHEMATIC SENSE VDDA Fig 15. External reference (p- (p-p) full-scale 11.3.2 Reference gain control The reference gain is programmable between − steps via the SPI ...
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... NXP Semiconductors 11.3.3 Common-mode output voltage (V A 0.1 μF filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. ...
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... NXP Semiconductors a. Sine clock input c. LVDS clock input Fig 19. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in voltage of the differential input stage is set via internal 5 kΩ resistors. Fig 20. Equivalent input circuit ADC1010S_SER_1 Preliminary data sheet ADC1010S series ...
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... NXP Semiconductors Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. ...
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... NXP Semiconductors The output resistance is 50 Ω and is the combination of the an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see 11 ...
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... NXP Semiconductors Table 14. LVDS_INT_TER[2:0] 000 001 010 011 100 101 110 111 11.5.3 Data valid (DAV) output clock A data valid output clock signal (DAV) can be used to capture the data delivered by the ADC1010S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in Figure 4 11 ...
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... NXP Semiconductors 11.5.7 Output codes versus input voltage Table 16. − INP < −1 −1.0000000 −0.9980469 −0.9960938 −0.9941406 −0.9921875 .... −0.0039063 −0.0019531 0.0000000 +0.0019531 +0.0039063 .... +0.9921875 +0.9941406 +0.9960938 +0.9980469 +1.0000000 > +1 11.6 Serial peripheral interface 11.6.1 Register description The ADC1010S serial interface is a synchronous serial communications port that allows for easy interfacing with many commonly-used microprocessors ...
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... NXP Semiconductors Table 18 Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses. The steps involved in a data transfer are as follows: 1 ...
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... NXP Semiconductors Fig 25. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR Fig 26. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS ADC1010S_SER_1 Preliminary data sheet ADC1010S series; CMOS or LVDS DDR digital outputs CS SDIO (CMOS LVDS DDR) ...
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Register allocation map Table 19. Register allocation map AddrHex Register name R/W Bit definition Bit 7 0005 Reset and R/W SW_RST operating mode 0006 Clock R/W - 0008 Internal reference R/W - 0011 Output data R/W - standard 0012 ...
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... NXP Semiconductors Table 20. Reset and operating mode control register (address 0005h) bit description Bit Symbol Access 7 SW_RST R RESERVED[2: OP_MODE[1:0] R/W Table 21. Clock control register (address 0006h) bit description Bit Symbol Access SE_SEL R/W 3 DIFF_SE R CLKDIV R/W 0 DCS_EN ...
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... NXP Semiconductors Table 22. Internal reference control register (address 0008h) bit description Bit Symbol Access INTREF_EN R INTREF[2:0] R/W Table 23. Output data standard control register (address 0011h) bit description Bit Symbol LVDS_CMOS 3 OUTBUF 2 OUTBUS_SWAP DATA_FORMAT[1:0] ADC1010S_SER_1 Preliminary data sheet ADC1010S series ...
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... NXP Semiconductors Table 24. Output clock register (address 0012h) bit description Bit Symbol DAVINV DAVPHASE[2:0] Table 25. Offset register (address 0013h) bit description Bit Symbol DIG_OFFSET[5:0] Table 26. Test pattern register 1 (address 0014h) bit description Bit Symbol ...
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... NXP Semiconductors Table 28. Test pattern register 3 (address 0016h) bit description Bit Symbol TESTPAT_USER[1: Table 29. Fast OTR register (address 0017h) bit description Bit Symbol FASTOTR FASTOTR_DET[2:0] Table 30. CMOS output register (address 0020h) bit description Bit Symbol ...
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... NXP Semiconductors Table 31. LVDS DDR output register 1 (address 0021h) bit description Bit Symbol Access DAVI_x2_EN R DAVI[1:0] R/W 2 DATAI_x2_EN R DATAI[1:0] R/W Table 32. LVDS DDR output register 2 (address 0022h) bit description Bit Symbol BIT_BYTE_WISE LVDS_INTTER[2:0] ADC1010S_SER_1 Preliminary data sheet ADC1010S series ...
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... NXP Semiconductors 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 0.85 mm terminal 1 index area terminal 1 40 index area Dimensions (1) Unit max 1.00 0.05 0.30 mm nom 0.85 0.02 0.21 0.2 min 0.80 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 13. Revision history Table 33. Revision history Document ID Release date ADC1010S_SER_1 20100409 ADC1010S_SER_1 Preliminary data sheet ADC1010S series; CMOS or LVDS DDR digital outputs Data sheet status Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 9 April 2010 ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... ADC1010S series; CMOS or LVDS DDR digital outputs NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.1 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.2 Clock and digital output timing . . . . . . . . . . . . 10 10 ...