adc1010s125hn/c1 NXP Semiconductors, adc1010s125hn/c1 Datasheet - Page 29

• Manufacturer Part Number: adc1010s125hn/c1
• Description: Single 10-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 24.
Table 25.
Table 26.
Table 27.
ADC1010S_SER_1
Preliminary data sheet
Bit
7 to 4
3
2 to 0
Bit
7 to 6
5 to 0
Bit
7 to 3
2 to 0
Bit
7 to 0
Symbol
-
DAVINV
DAVPHASE[2:0]
Symbol
-
DIG_OFFSET[5:0]
Symbol
-
TESTPAT_SEL[2:0]
Symbol
TESTPAT_USER[9:2]
Output clock register (address 0012h) bit description
Offset register (address 0013h) bit description
Test pattern register 1 (address 0014h) bit description
Test pattern register 2 (address 0015h) bit description
Access
R/W
R/W
Access
R/W
Access
R/W
Access
R/W
All information provided in this document is subject to legal disclaimers.
Value
0000
0
1
000
001
010
011
100
101
110
111
Value
00
011111
...
000000
...
100000
Value
00000
000
001
010
011
100
101
110
111
Rev. 01 — 9 April 2010
Value
00000000 custom digital test pattern (bits 9 to 2)
output clock data valid (DAV) polarity
Description
not used
DAV phase select
normal
inverted
output clock shifted (ahead) by 3 ns
output clock shifted (ahead) by 2.5 ns
output clock shifted (ahead) by 2 ns
output clock shifted (ahead) by 1.5 ns
output clock shifted (ahead) by 1 ns
output clock shifted (ahead) by 0.5 ns
default value as defined in timing section
output clock shifted (delayed) by 0.5 ns
ADC1010S series; CMOS or LVDS DDR digital outputs
Description
not used
digital test pattern select
Description
not used
digital offset adjustment
...
0
...
off
mid scale
−FS
+FS
toggle ‘1111..1111’/’0000..0000’
custom test pattern
‘1010..1010.’
‘010..1010’
+31 LSB
−32 LSB
Description
ADC1010S series
© NXP B.V. 2010. All rights reserved.
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