adc1010s125hn/c1 NXP Semiconductors, adc1010s125hn/c1 Datasheet - Page 13

• Manufacturer Part Number: adc1010s125hn/c1
• Description: Single 10-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1010S_SER_1
Preliminary data sheet
11.1.2 Operating mode selection
11.1.3
11.1.4
11.2.1 Input stage
11.2 Analog inputs
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO at the instant a transition is triggered by a falling
edge on CS.
The active ADC1010S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see
described in
Table 10.
Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see
HIGH, otherwise CMOS is selected.
Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
The analog input of the ADC1010S supports differential or single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
The equivalent circuit of the sample and hold input stage, including Electrostatic
Discharge (ESD) protection and circuit and package parasitics, is shown in
Pin PWD
0
0
1
1
Fig 7. Control mode selection
Table
I(cm)
Operating mode selection via pin PWD and OE
23) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is
Table
) on pins INP and INM set to 0.5V
SCLK/DFS
SDIO/ODS
All information provided in this document is subject to legal disclaimers.
10.
CS
Pin OE
0
1
0
1
Rev. 01 — 9 April 2010
two's complement
Pin control mode
Table
Data format
LVDS DDR
Table
ADC1010S series; CMOS or LVDS DDR digital outputs
20) or using pins PWD and OE in Pin control mode, as
23) or using pin DFS in Pin control mode (offset
offset binary
Data format
Operating mode
Power-up
Power-up
Sleep
Power-down
CMOS
Section 11.3
DDA
.
ADC1010S series
R/W
SPI control mode
and
W1
Table 22
W0
005aaa039
Output high-Z
no
yes
yes
yes
A12
further details).
© NXP B.V. 2010. All rights reserved.
Figure
8.
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