adc1010s125hn/c1 NXP Semiconductors, adc1010s125hn/c1 Datasheet - Page 12

• Manufacturer Part Number: adc1010s125hn/c1
• Description: Single 10-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
11. Application information
ADC1010S_SER_1
Preliminary data sheet
11.1.1 SPI and Pin control modes
10.3 SPI timings
11.1 Device control
Table 9.
[1]
The ADC1010S can be controlled via SPI or directly via the I/O pins (PIN control mode).
The device enters Pin control mode at power-up, and remains in this mode as long as pin
CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS LOW. Once SPI control mode has been
enabled, the device will remain in this mode. The transition from Pin control mode to SPI
control mode is illustrated in
Symbol
t
t
t
t
t
f
w(SCLK)
w(SCLKH)
w(SCLKL)
su
h
clk(max)
Fig 6.
Typical values measured at V
values are across the full temperature range T
SPI timing
SCLK
SPI timings characteristics
SDIO
Parameter
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
hold time
maximum clock frequency
CS
All information provided in this document is subject to legal disclaimers.
t
su
R/W
Rev. 01 — 9 April 2010
DDA
Figure
W1
t
h
= 3 V, V
t
su
ADC1010S series; CMOS or LVDS DDR digital outputs
W0
t
7.
w(SCLK)
DDO
= 1.8 V, T
amb
A12
Conditions
data to SCLK HIGH
CS to SCLK HIGH
data to SCLK HIGH
CS to SCLK HIGH
= −40 °C to +85 °C at V
amb
A11
t
w(SCLKL)
= 25 °C and C
ADC1010S series
t
w(SCLKH)
D2
L
40
16
16
-
Min
5
5
2
2
D1
DDA
= 5 pF; minimum and maximum
= 3 V, V
Typ
-
-
-
-
-
-
-
-
D0
© NXP B.V. 2010. All rights reserved.
t
h
005aaa065
DDO
Max
-
-
-
-
-
-
-
25
= 1.8 V
12 of 36
Unit
ns
ns
ns
ns
ns
ns
ns
MHz