adc1010s125hn/c1 NXP Semiconductors, adc1010s125hn/c1 Datasheet - Page 24

• Manufacturer Part Number: adc1010s125hn/c1
• Description: Single 10-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Cmos Or Lvds Ddr Digital Outputs
• Manufacturer: NXP Semiconductors

NXP Semiconductors
ADC1010S_SER_1
Preliminary data sheet
Fig 24. SPI mode timing
SCLK
SDIO
CS
R/W W1
11.6.2 Default modes at start-up
W0 A12 A11 A10
Table 18.
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
During circuit initialization, it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS will trigger a transition to SPI control mode. When the ADC1010S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see
can be changed via bit LVDS/CMOS
When the ADC1010S enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] in
W1
0
0
1
1
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but will always
4. A rising edge on CS indicates the end on data transmission.
communications.
be a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
A9
Instruction bytes
A8
Number of data bytes to be transferred after the instruction bytes
W0
0
1
0
1
A7
A6
All information provided in this document is subject to legal disclaimers.
A5
1 byte
2 bytes
3 bytes
4 bytes or more
Number of bytes transmitted
A4
Table
Rev. 01 — 9 April 2010
A3
Figure
A2
23.
A1
ADC1010S series; CMOS or LVDS DDR digital outputs
A0
25). Once in SPI control mode, the output data standard
D7
in
D6
Table 23
D5
Register N (data)
D4
.
D3
D2
ADC1010S series
D1
D0
D7
D6
D5
Register N + 1 (data)
D4
© NXP B.V. 2010. All rights reserved.
D3
D2
D1
005aaa062
D0
24 of 36