adc1010s125hn/c1 NXP Semiconductors, adc1010s125hn/c1 Datasheet - Page 31

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adc1010s125hn/c1

Manufacturer Part Number
adc1010s125hn/c1
Description
Single 10-bit Adc; 65 Msps, 80 Msps, 105 Msps Or 125 Msps; Cmos Or Lvds Ddr Digital Outputs
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
Table 31.
Table 32.
ADC1010S_SER_1
Preliminary data sheet
Bit
7 to 6
5
4 to 3
2
1 to 0
Bit
7 to 4
3
2 to 0
Symbol
-
DAVI_x2_EN
DAVI[1:0]
DATAI_x2_EN
DATAI[1:0]
LVDS_INTTER[2:0]
Symbol
-
BIT_BYTE_WISE
LVDS DDR output register 1 (address 0021h) bit description
LVDS DDR output register 2 (address 0022h) bit description
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
All information provided in this document is subject to legal disclaimers.
Value
00
0
1
00
01
10
11
0
1
00
01
10
11
Value
0000
0
1
000
001
010
011
100
101
110
111
Rev. 01 — 9 April 2010
Description
not used
double LVDS current for DAV LVDS buffer
LVDS current for DAV LVDS buffer
double LVDS current for DATA LVDS buffer
LVDS current for DATA LVDS buffer
disabled
enabled
3.5 mA
4.5 mA
1.25 mA
2.5 mA
disabled
enabled
3.5 mA
4.5 mA
1.25 mA
2.5 mA
Description
not used
DDR mode for LVDS output
internal termination for LVDS buffer (DAV and DATA)
ADC1010S series; CMOS or LVDS DDR digital outputs
bit wise (even data bits output on DAV rising edge/odd data
bits output on DAV falling edge)
byte wise (MSB data bits output on DAV rising edge/LSB data
bits output on DAV falling edge)
no internal termination
300 Ω
180 Ω
110 Ω
150 Ω
100 Ω
81 Ω
60 Ω
ADC1010S series
© NXP B.V. 2010. All rights reserved.
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