ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 14

• Manufacturer Part Number: ep1c6t144i8es
• Description: Cyclone Fpga Family
• Manufacturer: Altera Corporation

Cyclone FPGA Family Data Sheet
Figure 7. LE in Dynamic Arithmetic Mode
Note to
(1)
14
LAB Carry-In
Carry-In0
Carry-In1
The addnsub signal is tied to the carry input for the first LE of a carry chain only.
data1
data2
data3
(LAB Wide)
addnsub
Figure
(1)
7:
Carry-Out0
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in dynamic arithmetic mode. The carry-select chain uses the
redundant carry calculation to increase the speed of carry functions. The
LE is configured to calculate outputs for a possible carry-in of 0 and carry-
in of 1 in parallel. The carry-in0 and carry-in1 signals from a lower-
order bit feed forward into the higher-order bit via the parallel carry chain
and feed into both the LUT and the next portion of the carry chain. Carry-
select chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel pre-
computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delays between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Cyclone architecture
to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
LUT
LUT
LUT
LUT
Carry-Out1
Register chain
connection
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
Register Feedback
sclear
(LAB Wide)
ADATA
ENA
D
ALD/PRE
aload
CLRN
Q
Preliminary Information
Altera Corporation
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
LUT chain
connection
Register
chain output