ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 92

• Manufacturer Part Number: ep1c6t144i8es
• Description: Cyclone Fpga Family
• Manufacturer: Altera Corporation

Cyclone FPGA Family Data Sheet
92
Decrease input delay to
internal cells
Decrease input delay to
input register
Increase delay to output
pin
Table 67. Cyclone IOE Programmable Delays on Row Pins
Parameter
On
Small
Medium
Large
On
On
Maximum Input & Output Clock Rates
Tables 68
pins in Cyclone devices.
Setting
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Table 68. Cyclone Maximum Input Clock Rate for Column Pins
I/O Standard
and
-6 Speed Grade
Min
69
show the maximum input clock rate for column and row
3,057
2,212
2,639
3,057
3,057
Max
556
-6 Speed
Grade
-7 Speed Grade
Min
304
220
213
166
304
100
100
134
134
231
3,362
2,433
2,902
3,362
3,362
Max
611
-7 Speed
Grade
304
220
213
166
304
100
100
134
134
231
-8 Speed Grade
Min
Preliminary Information
-8 Speed
Grade
Altera Corporation
304
220
213
166
304
100
100
134
134
231
3,668
2,654
3,166
3,668
3,668
Max
667
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Unit
ps
ps
ps
ps
ps
ps