ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 87

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ep1c6t144i8es

Manufacturer Part Number
ep1c6t144i8es
Description
Cyclone Fpga Family
Manufacturer
Altera Corporation
Datasheet
Preliminary Information
Altera Corporation
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
3.3-V PCI
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS
Table 60. Cyclone I/O Standard Column Pin Input Delay Adders
Table 61. Cyclone I/O Standard Row Pin Input Delay Adders
I/O Standard
I/O Standard
(1)
Tables 60
row I/O pins for all packages. If an I/O standard is selected other than
LVTTL 24 mA with a fast slew rate, add the selected delay to the external
t
CO
-6 Speed Grade
Min
-6 Speed Grade
Min
and t
SU
through
I/O parameters shown in
Max
Max
214
326
214
326
28
221
221
264
264
197
28
221
221
264
264
197
0
0
0
0
0
65
show the adder delays associated with column and
-7 Speed Grade
Min
-7 Speed Grade
Min
Max
Max
235
358
235
358
30
244
244
291
291
217
30
244
244
291
291
217
0
0
0
0
0
Tables 45
Cyclone FPGA Family Data Sheet
-8 Speed Grade
Min
-8 Speed Grade
Min
through 48.
Max
Max
256
391
256
391
33
266
266
317
317
237
33
266
266
317
317
237
0
0
0
0
0
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
87

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