mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 147

• Manufacturer Part Number: mc68hc908gr8b
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

RE — Receiver Enable Bit
RWU — Receiver Wakeup Bit
SBK — Send Break Bit
13.8.3 SCI Control Register 3
SCI control register 3:
Freescale Semiconductor
Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not
affect receiver interrupt flag bits. Reset clears the RE bit.
This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled.
The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out
of the standby state and clears the RWU bit. Reset clears the RWU bit.
Setting and then clearing this read/write bit transmits a break character followed by a 1. The 1 after the
break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter
continuously transmits break characters with no 1s between them. Reset clears the SBK bit.
•
•
•
1 = Receiver enabled
0 = Receiver disabled
1 = Standby state
0 = Normal operation
1 = Transmit break characters
0 = No break characters being transmitted
Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted
Enables these interrupts:
–
–
–
Parity error interrupts
Receiver overrun interrupts
Noise error interrupts
Framing error interrupts
Address:
Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is clear.
ENSCI is in SCI control register 1.
Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.
Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling
SBK before the preamble begins causes the SCI to send a break character
instead of a preamble.
Reset:
Read:
Write:
$0015
Bit 7
R8
U
Figure 13-12. SCI Control Register 3 (SCC3)
= Unimplemented
T8
U
6
MC68HC908GR8B Data Sheet, Rev. 3.0
R
5
0
NOTE
NOTE
NOTE
R
R
4
0
= Reserved
ORIE
3
0
NEIE
2
0
U = Unaffected
FEIE
1
0
PEIE
Bit 0
0
I/O Registers
147