mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 150

• Manufacturer Part Number: mc68hc908gr8b
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Communications Interface (SCI) Module
NF — Receiver Noise Flag Bit
FE — Receiver Framing Error Bit
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Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing
sequence.
caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next
flag-clearing sequence reads byte 3 in the SCDR instead of byte 2.
In applications that are subject to software latency or in which it is important to know which byte is lost
due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.
This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD pin. NF generates an
SCI error CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1
and then reading the SCDR. Reset clears the NF bit.
This clearable, read-only bit is set when a 0 is accepted as the stop bit. FE generates an SCI error CPU
interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and
then reading the SCDR. Reset clears the FE bit.
1 = Noise detected
0 = No noise detected
1 = Framing error detected
0 = No framing error detected
Figure 13-14
BYTE 1
BYTE 1
READ SCS1
READ SCDR
shows the normal flag-clearing sequence and an example of an overrun
SCRF = 1
OR = 0
BYTE 1
Figure 13-14. Flag Clearing Sequence
MC68HC908GR8B Data Sheet, Rev. 3.0
READ SCDR
READ SCS1
BYTE 2
BYTE 2
DELAYED FLAG CLEARING SEQUENCE
SCRF = 1
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
OR = 0
READ SCDR
READ SCS1
SCRF = 1
BYTE 2
OR = 0
BYTE 3
BYTE 3
READ SCDR
READ SCDR
READ SCS1
READ SCS1
SCRF = 1
SCRF = 1
BYTE 3
BYTE 3
OR = 1
OR = 0
BYTE 4
BYTE 4
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