mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 51

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mc68hc908gr8b

Manufacturer Part Number
mc68hc908gr8b
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
3.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
3.7.3 ADC Clock Register
The ADC clock register (ADCLK) selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADICLK — ADC Input Clock Select Bit
Freescale Semiconductor
ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal
ADC clock.
approximately 1 MHz.
ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
1 = Internal bus clock
0 = Oscillator output clock (CGMXCLK)
Address:
Address:
Table 3-2
Reset:
Reset:
Read:
Read:
Write:
Write:
$003D
$003E
ADIV2
Bit 7
AD7
Bit 7
1. X = Don’t care
0
0
shows the available clock configurations. The ADC clock should be set to
ADIV2
0
0
0
0
1
Figure 3-5. ADC Clock Register (ADCLK)
= Unimplemented
= Unimplemented
ADIV1
Figure 3-4. ADC Data Register (ADR)
AD6
6
0
6
0
Table 3-2. ADC Clock Divide Ratio
MC68HC908GR8B Data Sheet, Rev. 3.0
ADIV1
X
0
0
1
1
(1)
ADIV0
AD5
5
0
5
0
ADIV0
X
0
1
0
1
(1)
ADICLK
AD4
4
0
4
0
ADC input clock
ADC input clock
ADC input clock
ADC input clock
ADC input clock
AD3
3
0
3
0
0
ADC Clock Rate
AD2
2
0
2
0
0
1
2
4
8
16
AD1
1
0
1
0
0
Bit 0
AD0
Bit 0
0
0
0
I/O Registers
51

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