adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 26

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
Bits
[10:9]
8
1
0
Table 15. Fractional PLL Parameter Settings for f
MCLK Input (MHz)
8
12
13
14.4
19.2
19.68
19.8
24
26
27
Table 16. Fractional PLL Parameter Settings for f
MCLK Input (MHz)
8
12
13
14.4
19.2
19.68
19.8
24
26
27
Table 17. Integer PLL Parameter Settings for f
MCLK Input (MHz)
12.288
24.576
1
X = don’t care.
Bit Name
X[1:0]
Type
Lock
PLLEN
Input Divider (X)
1
1
1
2
2
2
2
2
2
2
Input Divider (X)
1
1
1
2
2
2
2
2
2
2
Input Divider (X)
1
1
Description
PLL input clock divider
00: X = 1 (default)
01: X = 2
10: X = 3
11: X = 4
PLL operation mode
0: Integer (default)
1: Fractional
PLL lock (read-only bit)
0: PLL unlocked (default)
1: PLL locked
PLL enable
0: PLL disabled (default)
1: PLL enabled
Integer (R)
5
3
3
6
4
4
4
3
3
3
Integer (R)
6
4
3
6
5
4
4
4
3
3
Integer (R)
4
2
S
= 48 kHz (PLL Output = 49.152 MHz = 1024 × f
S
S
= 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × f
= 48 kHz (PLL Output = 49.152 MHz = 1024 × f
Rev. 0 | Page 26 of 88
Denominator (M)
625
625
8125
125
125
1025
1375
625
8125
1875
Denominator (M)
125
125
1625
75
25
205
825
125
1625
1125
Denominator (M)
Don’t care
Don’t care
Numerator (N)
403
477
3849
34
88
604
772
477
3849
647
Numerator (N)
18
12
1269
62
3
204
796
12
1269
721
Numerator (N)
Don’t care
Don’t care
S
)
S
)
S
R2: PLL Control Setting (Hex)
0x007D 0012 3101
0x007D 000C 2101
0x0659 04F5 1901
0x004B 003E 3301
0x0019 0003 2B01
0x00CD 00CC 2301
0x0339 031C 2301
0x007D 000C 2301
0x0659 04F5 1B01
0x0465 02D1 1B01
)
R2: PLL Control Setting (Hex)
0x0271 0193 2901
0x0271 01DD 1901
0x1FBD 0F09 1901
0x007D 0022 3301
0x007D 0058 2301
0x0401 025C 2301
0x055F 0304 2301
0x0271 01DD 1B01
0x1FBD 0F09 1B01
0x0753 0287 1B01
R2: PLL Control Setting (Hex)
0xXXXX XXXX 2001
0xXXXX XXXX 1001
1