adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 51

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

R1: PLL Control, 16,386 (0x4002)
Byte
0
1
2
3
4
5
Table 34. PLL Control Register
Byte
0
1
2
3
4
4
4
5
5
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[6:3]
[2:1]
0
1
0
Bit 7
Reserved
Bit Name
M[15:8]
M[7:0]
N[15:8]
N[7:0]
R[3:0]
X[1:0]
Type
Lock
PLLEN
Bit 6
Description
PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.
PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
M[15:8] (MSB)
00000000
…
00000000
…
11111111
PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.
PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.
N[15:8] (MSB)
00000000
…
00000000
…
11111111
PLL integer setting.
Setting
0010
0011
0100
0101
0110
0111
1000
PLL input clock divider.
Setting
00
01
10
11
Type of PLL. When set to integer mode, the values of M and N are ignored.
0 = integer (default).
1 = fractional.
PLL lock. This read-only bit is flagged when the PLL has finished locking.
0 = PLL unlocked (default).
1 = PLL locked.
PLL enable.
0 = PLL disabled (default).
1 = PLL enabled.
Bit 5
Reserved
R[3:0]
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Bit 4
M[7:0] (LSB)
00000000
…
11111101
…
11111111
N[7:0] (LSB)
00000000
…
00001100
…
11111111
Value of R
2 (default)
3
4
5
6
7
8
Value of X
1 (default)
2
3
4
M[15:8]
N[15:8]
M[7:0]
N[7:0]
Bit 3
Value of M
0
…
253 (default)
…
65,535
Value of N
0
…
12 (default)
…
65,535
Bit 2
X[1:0]
Bit 1
Lock
ADAU1461
Bit 0
Type
PLLEN