adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 36

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
CONTROL PORTS
The ADAU1461 can operate in one of two control modes:
•
•
The ADAU1461 has both a 4-wire SPI control port and a
2-wire I
registers. The part defaults to I
SPI control mode by pulling the CLATCH pin low three times.
The control port is capable of full read/write operation for all
addressable registers. The ADAU1461 must have a valid master
clock in order to write to all registers except for Register R0
(Address 0x4000) and Register R1 (Address 0x4002).
All addresses can be accessed in both a single-address mode
or a burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/ W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
register location within the ADAU1461. This subaddress must
be two bytes long because the memory locations within the
ADAU1461 are directly addressable and their sizes exceed the
range of single-byte addressing. All subsequent bytes (starting
with Byte 3) contain the data, such as control port data, program
data, or parameter data. The number of bytes per word depends
on the type of data that is being written.
The ADAU1461 has several mechanisms for updating signal pro-
cessing parameters in real time without causing pops or clicks. If
large blocks of data need to be downloaded, the output of the DSP
core can be halted (using the DSPRUN bit in the DSP run register,
Address 0x40F6), new data can be loaded, and the device can be
restarted. This is typically done during the booting sequence at
start-up or when loading a new program into RAM.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 19 describes these
multiple functions.
Table 19. Control Port Pin Functions
Pin Name
SCL/CCLK
SDA/COUT
ADDR1/CDATA
ADDR0/CLATCH
BURST MODE WRITING AND READING
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous registers. This increment happens
automatically after a single-word write or read unless a stop condi-
tion is encountered (I
burst write starts like a single-word write, but following the first
data-word, the data-word for the next immediate address can be
written immediately without sending its two-byte address.
I
SPI control
2
C control
2
C bus control port. Both ports can be used to set the
I
SCL: input clock
SDA: open-collector
input/output
I
I
2
2
2
C Address Bit 1: input
C Address Bit 0: input
C Mode
2
C) or CLATCH is brought high (SPI). A
2
C mode, but it can be put into
SPI Mode
COUT: output
CLATCH: input
CCLK: input clock
CDATA: input
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The registers in the ADAU1461 are one byte wide with the
exception of the PLL control register, which is six bytes wide.
The autoincrement feature knows the word length at each
subaddress, so the subaddress does not need to be specified
manually for each address in a burst write.
The subaddresses are autoincremented by 1 following each read
or write of a data-word, regardless of whether there is a valid regis-
ter or RAM word at that address. Address holes in the register
map can be written to or read from without consequence. In the
ADAU1461, these address holes exist at Address 0x4001, Address
0x4003 to Address 0x4007, Address 0x402E, Address 0x4032 to
Address 0x4035, Address 0x4037 to Address 0x40BF, Address
0x40C5, Address 0x40CA to Address 0x40CF, Address 0x40D5
to Address 0x40EA, and Address 0x40EC to Address 0x40F1. A
single-byte write to these registers is ignored by the ADAU1461,
and a read returns a single byte 0x00.
I
The ADAU1461 supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1461 and the system I
In I
meaning that it cannot initiate a data transfer. Each slave device
is recognized by a unique address. The address and R/ W byte
format is shown in
seven bits of the I
ADAU1461 are set by the levels on the ADDR1 and ADDR0
pins. The LSB of the address—the R/
read or write operation. Logic Level 1 corresponds to a read
operation, and Logic Level 0 corresponds to a write operation.
Table 20. ADAU1461 I
Bit 0
0
The SDA and SCL pins should each have a 2 kΩ pull-up resistor
on the line connected to it. The voltage on these signal lines
should not be higher than IOVDD (3.3 V).
Addressing
Initially, each device on the I
monitors the SDA and SCL lines for a start condition and
the proper address. The I
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
R/ W bit) MSB first. The device that recognizes the transmitted
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition.
2
C PORT
2
C mode, the ADAU1461 is always a slave on the bus,
Bit 1
1
Bit 2
1
2
C write. Bits[5:6] of the I
Table 20
2
Bit 3
1
C Address and Read/ Write Byte Format
2
C master initiates a data transfer by
. The address resides in the first
2
C bus is in an idle state and
Bit 4
0
W bit—specifies either a
Bit 5
ADDR1
2
C master controller.
2
2
C-compatible)
C address for the
Bit 6
ADDR0
Bit 7
R/W