adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 80

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
R60: Serial Data/GPIO Pin Configuration, 16,628 (0x40F4)
The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1,
these pins are configured as GPIO interfaces to the SigmaDSP. If these bits are set to 0, they are configured as serial data I/O port pins.
Bit 7
Table 83. Serial Data/GPIO Pin Configuration Register
Bits
3
2
1
0
R61: DSP Enable, 16,629 (0x40F5)
Bit 7
Table 84. DSP Enable Register
Bits
0
R62: DSP Run, 16,630 (0x40F6)
Bit 7
Table 85. DSP Run Register
Bits
0
Bit Name
LRGP3
BGP2
SDOGP1
SDIGP0
Bit Name
DSPEN
Bit Name
DSPRUN
Bit 6
Bit 6
Bit 6
Description
LRCLK or GPIO3 pin configuration select.
0 = LRCLK enabled (default).
1 = GPIO3 enabled.
BCLK or GPIO2 pin configuration select.
0 = BCLK enabled (default).
1 = GPIO2 enabled.
ADC_SDATA or GPIO1 pin configuration select.
0 = ADC_SDATA enabled (default).
1 = GPIO1 enabled.
DAC_SDATA or GPIO0 pin configuration select.
0 = DAC_SDATA enabled (default).
1 = GPIO0 enabled.
Description
Enables the DSP. Set this bit before writing to the parameter RAM and before setting the DSPRUN bit in
Register R62 (Address 0x40F6).
0 = DSP disabled (default).
1 = DSP enabled.
Description
Run the DSP. Set the DSPEN bit in Register R61 (Address 0x40F5) before setting this bit.
0 = DSP off (default).
1 = run the DSP.
Reserved
Bit 5
Bit 5
Bit 5
Bit 4
Bit 4
Bit 4
Reserved
Reserved
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Bit 3
LRGP3
Bit 3
Bit 3
Bit 2
BGP2
Bit 2
Bit 2
Bit 1
SDOGP1
Bit 1
Bit 1
Bit 0
SDIGP0
Bit 0
DSPEN
Bit 0
DSPRUN