adau1461 Analog Devices, Inc., adau1461 Datasheet - Page 76

• Manufacturer Part Number: adau1461
• Description: Sigmadsp Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll Adau1461
• Manufacturer: Analog Devices, Inc.

ADAU1461
R43 to R47: Cyclic Redundancy Check Registers, 16,576 to 16,580 (0x40C0 to 0x40C4)
The cyclic redundancy check (CRC) constantly checks the validity of the program RAM contents. SigmaStudio generates a 32-bit hash
sum, which must be written to four consecutive read-only 8-bit register locations. CRC must then be enabled. Every 1024 frames (21 ms
at 48 kHz), the IC generates its own 32-bit code and compares it to the one stored in these registers. If the codes do not match, a GPIO pin
is set high (CRC flag). This output flag must be enabled using the output CRC error sticky setting in the GPIO pin control register (see
Table 77). The 1-bit CRC error flag is reset when the CRCEN bit goes low. For example, a GPIO pin can be connected to an interrupt pin
on an external microcontroller, which triggers a rewrite of the corrupted memory.
By default, CRC is disabled (the CRCEN bit is set to 0). To enable continuous CRC checking, the user can set the CRCEN bit to 1 after
loading a program and sending the correct CRC, which is calculated by SigmaStudio. If an error occurs, it can be cleared by setting the
CRCEN bit low, fixing the error (presumably by reloading the program), and then setting the CRCEN bit high again.
Address
0x40C0
0x40C1
0x40C2
0x40C3
0x40C4
Table 76. Cyclic Redundancy Check Registers
Register
R43
R44
R45
R46
R47
Bit 7
Decimal
16,576
16,577
16,578
16,579
16,580
Address
Hex
0x40C0
0x40C1
0x40C2
0x40C3
0x40C4
Bit 6
Bit Name
CRC[31:24]
CRC[23:16]
CRC[15:8]
CRC[7:0]
CRCEN
Bit 5
Description
CRC hash sum, Bits[31:24] (read-only register)
CRC hash sum, Bits[23:16] (read-only register)
CRC hash sum, Bits[15:8] (read-only register)
CRC hash sum, Bits[7:0] (read-only register)
CRC enable
0 = disabled (default)
1 = enabled
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Bit 4
Reserved
CRC[31:24]
CRC[23:16]
CRC[15:8]
CRC[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
CRCEN