m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 199

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(3) Isochronous Transfer: Endpoints 1 to 4 Receive
When endpoints 1 to 4 OUT are used for isochronous transfer, ISO bit of USB endpoint x(x=1 to 4)
OUT control and status register is set to “1” for isochronous transfer setting.
When there is a packet space in OUT FIFO, on receiving the OUT token from the host CPU, the data
are received. At this time, the OUT FIFO status is updated, the endpoint x OUT interrupt request
occurs. When an error is detected in the received packet, simultaneously, the DATA_ERR flag is set
to “1”. (Error checks such as CRC check, conforming to USB2.0 specification, are automatically
performed.)
When the OUT token is received from the host CPU while there are already data in OUT FIFO and
packet data cannot be received, an overrun error occurs. At this time, the OVER_RUN flag is set to
“1”.
Further, when a packet, which size exceeds the maximum packet size, is transmitted from the host
CPU, the FORCE_STALL flag is set to “1” without receiving the data. While error interrupt has been
enabled by USB function interrupt enable register, an error interrupt request occurs when any one of
the OVER_RUN flag, FORCE_STALL flag or DATA_ERR flag is set to “1” (INTST8 is set to “1”).
The fetch procedure of endpoint x OUT receive data in the isochronous transfer is same as the bulk
transfer.
Refer to “
continuous transfer is valid for the bulk transfer only.)
Setting of Transfer Type
Receive Operation
Fetch of Receive Data
Fetch of Receive Data” of “(2) Bulk Transfer: Endpoints 1 to 4 Receive”. (Although
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2. USB function