m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 349

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
4.4 Connectable Memories
4.4.1 Operation Frequency and Access Time
Connectable memories depend upon the BCLK frequency f(BCLK). The frequency of f(BCLK) is equal to
that of the BCLK, and is contingent on the oscillator's frequency and on the settings in the system clock
select bits (bit 6 of address 0006
The following are the conditional equations for the connections. Meet these conditions minimally. Fig-
ures 4.4.1 and 4.4.2 show the relation between the frequency of BCLK and memory.
(1) Read cycle time (tCR)/write cycle time (tCW)
(2) Address access time [ta(A)]
(3) Chip select access time [ta(S)]
Read cycle time (tCR) and write cycle time (tCW) must satisfy the following conditional expressions:
• With the Wait option cleared
• With the Wait option selected
Address access time [ta(A)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
• With the Wait option selected
Chip select access time [ta(S)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
• With the Wait option selected
tCR < 10
(When CSxW = 1 read: one cycle of BCLK write: two cycles of BCLK)
tCR < (m+1)
(When CSxW = 0 and the number of the expansion waits is selected by the CSExW bit)
(m denotes the number of Wait states: m = “1” when 1 wait selected, “m = 2” when 2 waits selected,
and “m = 3” when 3 waits selected)
ta(A) < 10
ta(A) < (m+1)
ta(S) < 10
ta(S) < (m+1)
(m = “1” when 1 wait selected, “m = 2” when 2 waits selected, and “m = 3” when 3 waits selected)
(m = “1” when 1 wait selected, “m = 2” when 2 waits selected, and “m = 3” when 3 waits selected)
*80(ns) = td(BCLK – AD) + tsu(DB – RD) – th(BCLK – RD)
*80(ns) = td(BCLK – CS) + tsu(DB – RD) – th(BCLK – RD)
9
/f(BCLK) and tCW < 2
9
= (address output delay time) + (data input setup time) – (RD signal output hold time)
9
= (chip select output delay time) + (data input setup time) – (RD signal output hold time)
/f(BCLK) – 80(ns)*
/f(BCLK) – 80(ns)*
page 340 of 354
10
10
10
9
/f(BCLK) and tCW < (m+1)
9
9
/f(BCLK) – 80(ns)*
/f(BCLK) – 80(ns)*
16
, and bits 6 and 7 of address 0007
10
9
/f(BCLK)
10
9
/f(BCLK)
16
).
4. External Buses