m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 82

• Manufacturer Part Number: m5m51016btp
• Description: Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
• Manufacturer: Renesas Electronics Corporation.

M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Operation
Note
2.4.5 Operation of Serial I/O (transmission used for SIM interface)
In transmitting data in UARTi (i=0 to 3) mode (used for SIM interface), choose functions from those listed
in Table 2.4.6. Operations of the circled items are described below. Figure 2.4.13 shows the operation
timing, and Figures 2.4.14 and 2.4.15 show the set-up procedures.
Table 2.4.6. Choosed functions
(1) Setting the transmit enable bit and receive enable bit to “1” and writing transmission data to
(2) Transmission data held in the UARTi (i=0 to 3) transmit buffer register is transmitted to the
(3) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which
(4) If the transmission condition of the next data is ready when transmission is completed, a start
(5) If a parity error occurs, an L is output from the SIM card, and the RxDi (i=0 to 3) terminal turns
• Set the RxDi (i=0 to 3) pin's port direction register to input.
• Select N-channel open drain output for TxDi pin with data output select bit of UARTi (i=0 to 3)
• The parity error level is determined within a UARTi (i=0 to 3) transmission interrupt. When a
Transfer data
format
transmission interrupt request occurs, set the priority level of the transmission interrupt higher
than those of other interrupts so that the interrupt routine can be immediately carried out.
Either in the main routine or in an interrupt routine, the interrupt inhibition time has to be made
as short as possible.
transmit/receive control register 0.
the UARTi (i=0 to 3) transmit buffer register readies the data transmissible status. Set UARTi
(i=0 to 3) transfer interrupt for being enabled.
UARTi (i=0 to 3) transmit register. At this time, the first bit (the start bit) of the transmission
data is transmitted from the TxDi (i=0 to 3) pin. Then, data is transmitted, bit by bit, in se-
quence: LSB, ····, MSB, parity bit, and stop bit(s).
indicates that transmission is completed. At this time, the UARTi (i=0 to 3) transmit interrupt
request bit goes to “1”. The transfer clock stops at “H” level.
bit is generated following to stop bit(s), and the next data is transmitted.
to "L" level. Check the RxDi (i=0 to 3) terminal's level within the UARTi (i=0 to 3) transmission
interrupt routine, and if it is found to be at the "L" level, then handle the error.
Item
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O
Inverse format
Direct format
Set-up
Transfer clock
source
Item
O
External clock (CLKi pin)
Internal clock (f
Set-up
2. SIM interface
1
/f
8
/f
32
)