m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 54

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m5m51016btp

Manufacturer Part Number
m5m51016btp
Description
Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet

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M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Operation
2.3.2 Operation of Serial I/O (transmission in clock-synchronous serial I/O mode)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.3.1. Operations of the circled items are described below. Figure 2.3.5 shows the operation timing, and
Figures 2.3.6 and 2.3.7 show the set-up procedures.
(1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
(2) When input to the CTSi pin goes to “L” level, transmission starts (the CTSi pin must be
(3) In synchronization with the first falling edge of the transfer clock, transmission data held in the
(4) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
(5) If the next transmission data is set in the UARTi transmit buffer register while transmission is
Table 2.3.1. Choosed functions
CTS function
CLK polarity
Transfer clock
source
buffer register makes data transmissible status ready.
controlled on the reception side).
UARTi transmit buffer register is transmitted to the UARTi transmit register. At this time, the
UARTi transmit interrupt request bit goes to “1”. Also, the first bit of the transmission data is
transmitted from the TxDi pin. Then the data is transmitted bit by bit from the lower order in
synchronization with the falling edges.
which indicates that transmission is completed. The transfer clock stops at “H” level.
in progress (before the eighth bit has been transmitted), the data is transmitted in succession.
Item
page 45 of 354
O
O
O
________
CTS function enabled
Internal clock (f
External clock (CLKi pin)
CTS function disabled
Output transmission data at
the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
Set-up
1
/ f
8
/ f
32
)
T
polarity reverse bit
Transfer clock
Transmission
interrupt factor
Data logic select
function
X
D, R
X
Item
D I/O
2. Clock-Synchronous Serial I/O
O
O
O
O
LSB first
MSB first
No reverse
Reverse
No reverse
Reverse
Transmission buffer empty
Transmission complete
_______
Set-up

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