ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 10

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

6. Polling Circuit and Control Logic
7. Basic Clock Cycle of the Digital Circuitry
10
Atmel ATA5723C/ATA5724C/ATA5728C
The receiver is designed to consume less than 1 mA while being sensitive to signals from a
corresponding transmitter. This is achieved using the polling circuit. This circuit enables the
signal path periodically for a short time. During this time the bit-check logic verifies the pres-
ence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active
and transfers the data to the connected microcontroller. If there is no valid signal present, the
receiver is in sleep mode most of the time resulting in low current consumption. This condition
is called polling mode. A connected microcontroller is disabled during that time.
All relevant parameters of the polling logic can be configured by the connected microcon-
troller. This flexibility enables the user to meet the specifications in terms of current
consumption, system response time, data rate etc.
The receiver is very flexible with regards to the number of connection wires to the microcon-
troller. It can be either operated by a single bi-directional line to save ports to the connected
microcontroller or it can be operated by up to five uni-directional ports.
The complete timing of the digital circuitry and the analog filtering is derived from one clock.
This clock cycle T
28 or 30 circuit. According to
oscillator (f
quency of the local oscillator (f
ATA5728C is T
f
T
T
Most applications are dominated by three transmission frequencies: f
mainly used in USA, f
T
For calculation of T
“Electrical Characteristics Atmel ATA5724C, ATA5728C” on page
RF
Clk
Clk
Clk
• Timing of the polling circuit including bit check
• Timing of the analog and digital signal processing
• Timing of the register programming
• Frequency of the reset marker
• IF filter center frequency (fIF0)
• Application 315MHz band (f
• Application 868.3MHz band (f
• Application 433.92MHz band (f
= 433.92MHz. For Atmel ATA5723C the basic clock cycle is T
. For the aforementioned frequencies, T
= 2.0382µs for f
controls the following application-relevant parameters:
XTO
) is defined by the RF input signal (f
Clk
Clk
28/f
Clk
RF
is derived from the crystal oscillator (XTO) in combination with a divide by
Transmit
for applications using other frequency bands, see table in
= 315MHz.
XTO
giving T
= 868.3MHz and 433.92MHz in Europe. All timings are based on
Section 3. “RF Front-end” on page
XTO
LO
XTO
XTO
). The basic clock cycle for Atmel ATA5724C and Atmel
= 14.71875MHz, f
Clk
= 13.55234MHz, f
= 13.52875MHz, f
= 2.066µs for f
Clk
is given as:
RFin
LO
RF
LO
) which also defines the operating fre-
= 314.13MHz, T
LO
= 868.3MHz and T
= 867.35MHz, T
= 432.93MHz, T
5, the frequency of the crystal
37.
Clk
Clk
Transmit
Clk
= 2.0382µs)
Clk
= 30/f
= 2.066µs)
Clk
= 2.0696µs)
= 2.069µs for
9248A–RKE–09/11
= 315MHz is
Section 18.
REF
giving