ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 13

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

8.2
8.3
Figure 8-2.
9248A–RKE–09/11
Data_out (DATA)
Bit-check Mode
Configuring the Bit Check
IC_ACTIVE
(Number of checked Bits: 3)
Bit check
Dem_out
Timing Diagram for Complete Successful Bit Check
Start-up mode
T
In bit-check mode the incoming data stream is examined to distinguish between a valid signal
from a corresponding transmitter and signals due to noise. This is done by subsequent time
frame checks where the distances between 2 signal edges are continuously compared to a
programmable time window. The maximum number of these edge-to-edge tests, before the
receiver switches to receiving mode, is also programmable.
Assuming a modulation scheme that contains two edges per bit, two time frame checks verify
one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The max-
imum count of bits to be checked can be set to 0, 3, 6, or 9 bits using the variable N
the OPMODE register. This implies 0, 6, 12, and 18 edge-to-edge checks respectively. If
N
noise. In the presence of a valid transmitter signal, the bit check takes less time if N
set to a lower value. In polling mode, the bit-check time is not dependent on NBit-check.
ure 8-2
transferred to pin DATA.
According to
its. If the edge-to-edge time t
bit-check limit T
T
Figure 8-3.
Start-up
Lim_max
Bit-check
, the bit check is terminated and the receiver switches to sleep mode.
shows an example where three bits are tested successfully and the data signal is
is set to a higher value, the receiver is less likely to switch to receiving mode due to
Figure
Valid Time Window for Bit Check
Lim_max
Atmel ATA5723C/ATA5724C/ATA5728C
8-3, the time window for the bit check is defined by two separate time lim-
1/2 Bit
Dem_out
, the check continues. If t
1/2 Bit
Start-check mode
ee
is in between the lower bit-check limit T
T
Bit-check
1/2 Bit
T
T
Lim_max
Lim_min
Bit check ok
t
ee
1/2 Bit
1/f
Sig
1/2 Bit
ee
is smaller than T
1/2 Bit
Receiving mode
Lim_min
Lim_min
or t
and the upper
ee
Bit-check
Bit-check
exceeds
Fig-
13
in
is