ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 15

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 8-5.
Figure 8-6.
8.4
8.5
9248A–RKE–09/11
Duration of the Bit Check
Receiving Mode
(Lim_min = 14, Lim_max = 24)
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
IC_ACTIVE
Bit-check
Bit-check
Bit check
Dem_out
Bit check
Dem_out
counter
counter
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Timing Diagram for Failed Bit Check (Condition: CV_Lim
Start-up mode
Start-up mode
T
T
Start-up
Start-up
0
0
If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator
delivers random signals. The bit check is a statistical process and T
check. Therefore, an average value for T
T
causes a lower value for T
In the presence of a valid transmitter signal, T
nal, f
in a longer period for T
If the bit check was successful for all bits specified by N
ing mode. According to
DATA in that case, and the data clock is available after the start bit has been detected (see
Figure 9-1 on page
pin DATA or by the data clock at pin DATA_CLK. The receiver stays in that condition until it is
switched back to polling mode explicitly.
Bit-check
Sig
1 2
1 2
, and the count of the checked bits, N
depends on the selected baud-rate range and on T
3 4
3 4
5 6
5 6
7 1
1
Bit-check mode
Atmel ATA5723C/ATA5724C/ATA5728C
2 3
20). A connected microcontroller can be woken up by the negative edge at
T
2 3
Bit-check
Bit-check
4 5
Bit check failed (CV_Lim_ < Lim_min)
1/2 Bit
4 5
Figure 8-2 on page
Bit-check
6 7
Bit-check mode
6 7
requiring a higher value for the transmitter pre-burst T
8
T
Bit-check
8
9 10
resulting in a lower current consumption in polling mode.
9 10
11 12
1/2 Bit
11 12
13 14
Bit-check
15 16
Bit-check
Lim_max)
Bit-check
Bit check failed (CV_Lim
13, the internal data signal is switched to pin
17 18
Sleep mode
. A higher value for N
19 20
is given in the electrical characteristics.
T
is dependent on the frequency of that sig-
Sleep
0
21 22
Bit-check
23 24
, the receiver switches to receiv-
Clk
. A higher baud-rate range
Lim_max)
Sleep mode
Bit-check
T
Bit-check
Sleep
0
varies for each
thereby results
Preburst
.
15