ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 21

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

9248A–RKE–09/11
Figure 9-3.
Figure 9-4.
The delay of the data clock is calculated as follows: t
t
t
For the falling edge, t
Figure 9-6 on page 22
level of Data_Out, the data clock is issued after an additional delay t
Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load
at pin DATA is exceeded, the data clock disappears (see
32).
Data_out (DATA)
Data_out (DATA)
Delay1
Delay1
DATA_CLK
DATA_CLK
Dem_out
Dem_out
depends on the capacitive load C
is the delay between the internal signals Data_Out and Data_In. For the rising edge,
Data Clock Disappears Because of a Logical Error
Output of the Data Clock After a Successful Bit Check
Atmel ATA5723C/ATA5724C/ATA5728C
'1'
'1'
Receiving mode,
data clock control
Bit check ok
Delay1
bit check active
Receiving mode,
and
logic active
'1'
'1'
Figure 13-2 on page
depends additionally on the external voltage V
'1'
'1'
'0'
'1'
L
at pin DATA and the external pull-up resistor R
'1'
'1'
30). When the level of Data_In is equal to the
Start bit
Logical error (Manchester code violation)
'1'
'0'
Delay
Data
Data
= t
Section 14. “Data Interface” on page
'?'
'1'
Delay1
data clock control
Receiving mode,
logic active
+ t
'0'
'1'
Delay2
Delay2
'0'
'0'
.
Receiving mode,
bit check active
X
(see
'1'
'1'
Figure
'0'
'0'
9-5,
pup
21
.