ata5724p3c-tkqy ATMEL Corporation, ata5724p3c-tkqy Datasheet - Page 14

• Manufacturer Part Number: ata5724p3c-tkqy
• Description: Uhf Ask/fsk Receiver
• Manufacturer: ATMEL Corporation

Figure 8-4.
14
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
Bit-check
Bit check
Dem_out
counter
Atmel ATA5723C/ATA5724C/ATA5728C
Timing Diagram During Bit Check
Start-up mode
T
Start-up
0
For best noise immunity using a low span between T
is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A
“11111...” or a “10101...” sequence in Manchester or Bi-phase is suitable for this. A good com-
promise between receiver sensitivity and susceptibility to noise is a time window of ±30%
regarding the expected edge-to-edge time t
edge-to-edge time periods, the bit-check limits must be programmed according to the required
span.
The bit-check limits are determined by means of the formula below.
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using above formulas, Lim_min and Lim_max can be determined according to the required
T
imum edge-to-edge time t
“Digital Signal Processing” on page
maximum value of the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (N
prevent switching to receiving mode due to noise.
Figure
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during T
ing that period. When the bit check becomes active, the bit-check counter is clocked with the
cycle T
Figure 8-4
the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
the bit check fails as the value CV_Lim is lower than the limit Lim_min. The bit check also fails
if CV_Lim reaches Lim_max. This is illustrated in
Lim_min
Lim_max
Lim_min
1 2
XClk
, T
= Lim_min
8-4,
= (Lim_max – 1)
3 4
Lim_max
.
shows how the bit check proceeds if the bit-check counter value CV_Lim is within
T
Figure
5 6
XClk
7 8
and T
Startup
1 2
8-5, and
T
. The output of the ASK/FSK demodulator (Dem_out) is undefined dur-
XClk
XClk
3 4
. The time resolution defining T
ee
5 6
T
XClk
(t
DATA_L_min
Figure 8-6
7 8
1/2 Bit
9 10
Bit-check mode
16. The lower limit should be set to Lim_min
11 12
T
Bit-check
, t
13 14
DATA_H_min
illustrate the bit check for the bit-check limits
ee
Bit check ok
15 16
. Using pre-burst patterns that contain various
17 18
Figure
Lim_min
) is defined according to the
1 2
3 4
8-6.
Lim_min
and T
5 6
1/2 Bit
7 8
and T
Lim_max
9 10
Lim_max
11 12
is recommended. This
Bit check ok
13 14
is T
15
1 2
1/2 Bit
9248A–RKE–09/11
XClk
Section 8.6
Figure 8-5
3 4
. The min-
Bit-check
10. The
) to