71m6534h-igt Maxim Integrated Products, Inc., 71m6534h-igt Datasheet - Page 25
71m6534h-igt
Manufacturer Part Number
71m6534h-igt
Description
Energy Meter Ic
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.71M6534H-IGT.pdf
(124 pages)
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FDS_6533_6534_004
1.3.4 71M6533/71M6534-Specific Special Function Registers
Table 14
v1.1
EEDATA
EECTRL
ERASE
(FLSH_ERASE)
FL_BANK[2:0]
PGADDR
(FLSH_PGADR)
FLSHCRL
(Alternate
Register
Name)
shows the location and description of the 71M6533/71M6534-specific SFRs.
CKCON[2:0]
000
001
010
011
100
101
110
111
0x9E
0x9F
0x94
0xB6[2:0]
0xB7
0xB2[0]
0xB2[1]
0xB2[4]
0xB2[5]
0xB2[6]
0xB2[7]
Address
SFR
© 2007-2009 TERIDIAN Semiconductor Corporation
Table 14: 71M6533/71M6534 Specific SFRs
Stretch
FLSH_PWE
FLSH_MEEN
WRPROT_CE
WRPROT_BT
SECURE
PREBOOT
Table 13: Stretch Memory Cycle Width
Value
Bit Field
0
1
2
3
4
5
6
7
Name
memaddr
Read Signal Width
1
2
3
4
5
6
7
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
R
Description
I
I
Section
tion of the command and status bits available
for EECTRL.
This register is used to initiate either the Flash
Mass Erase cycle or the Flash Page Erase cycle.
See the
Flash Bank Selection.
Flash Page Erase Address register. Contains
the flash memory page address (page 0 through
page 127) that will be erased (default = 0x00).
Must be re-written for each new Page Erase
cycle.
Program Write Enable:
Mass Erase Enable:
Must be re-written for each new Mass Erase cycle.
Protects flash from address CE_LCTN*1024 to
the end of memory from flash page erase.
Protects flash from address 0 to address
BOOT_SIZE*1024 from flash page erase.
Enables security provisions that prevent external
reading of flash memory and CE program RAM.
This bit is reset on chip reset and may only be set.
Attempts to write zero are ignored.
Indicates that the preboot sequence is active.
2
2
memrd
C EEPROM interface data register.
C EEPROM interface control register. See
1: MOVX @DPTR,A moves A to Program
1: Mass Erase enabled.
0: MOVX commands refer to XRAM Space,
0: Mass Erase disabled (default).
1
2
3
4
5
6
7
8
Space (Flash) @ DPTR.
normal operation (default).
1.4.10 EEPROM Interface
Flash Memory
memaddr
Write Signal Width
2
3
4
5
6
7
8
9
71M6533/71M6534 Data Sheet
section for details.
memwr
1
1
2
3
4
5
6
7
for a descrip-
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